Joan Carletta

2008
22	EE	Firas Hassan, Joan Carletta: High throughput JPEG2000 compatible encoder for high dynamic range images. ICIP 2008: 1424-1427
2007
21	EE	Firas Hassan, Joan Carletta: A real-time FPGA-based architecture for a Reinhard-like tone mapping operator. Graphics Hardware 2007: 65-71
20	EE	Firas Hassan, Joan Carletta: A High Throughput Encoder for High Dynamic Range Images. ICIP (6) 2007: 213-216
2006
19	EE	Hima B. Damecharla, Kamal K. Varma, Joan Carletta, Amy E. Bell: FPGA implementation of a parallel EBCOT tier-1 encoder that preserves coding efficiency. ACM Great Lakes Symposium on VLSI 2006: 266-271
18	EE	Krishnaraj Varma, Amy E. Bell, Hima B. Damecharla, Joan Carletta: A Fast JPEG2000 EBCOT Tier-1 Architecture That Preserves Coding Efficiency. ICIP 2006: 3297-3300
17	EE	Kishore A. Kotteri, Amy E. Bell, Joan Carletta: Multiplierless filter Bank design: structures that improve both hardware and image compression performance. IEEE Trans. Circuits Syst. Video Techn. 16(6): 776-780 (2006)
2005
16	EE	Sankar Barua, Joan Carletta, Kishore A. Kotteri, Amy E. Bell: An efficient architecture for lifting-based two-dimensional discrete wavelet transforms. Integration 38(3): 341-352 (2005)
2004
15	EE	Sankar Barua, Joan Carletta, Kishore A. Kotteri, Amy E. Bell: An efficient architecture for lifting-based two-dimensional discrete wavelet transforms. ACM Great Lakes Symposium on VLSI 2004: 61-66
2003
14	EE	Joan Carletta, Robert J. Veillette, Frederick W. Krach, Zhengwei Fang: Determining appropriate precisions for signals in fixed-point IIR filters. DAC 2003: 656-661
13	EE	Joan Carletta, Robert J. Veillette, Frederick W. Krach, Zhengwei Fang: Implementation of digital fixed-point approximations to continuous-time IIR filters. FPGA 2003: 241
2002
12	EE	Joan Carletta, M. D. Rayman: Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs. FPL 2002: 886-896
2001
11	EE	Mehrdad Nourani, Joan Carletta, Christos A. Papachristou: Integrated test of interacting controllers and datapaths. ACM Trans. Design Autom. Electr. Syst. 6(3): 401-422 (2001)
2000
10	EE	Mehrdad Nourani, Joan Carletta, Christos A. Papachristou: Synthesis-for-testability of controller-datapath pairs that use gated clocks. DAC 2000: 613-618
9	EE	Joan Carletta, Christos A. Papachristou, Mehrdad Nourani: Detecting Undetectable Controller Faults Using Power Analysis. DATE 2000: 723-728
8	EE	Elie Yarack, Joan Carletta: An Evaluation of Move-Based Multi-Way Partitioning Algorithms. ICCD 2000: 363-369
7	EE	John T. Welch, Joan Carletta: A Direct Mapping FPGA Architecture for Industrial Process Control Applications. ICCD 2000: 595-598
1999
6	EE	Joan Carletta, Mehrdad Nourani, Christos A. Papachristou: Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs. DATE 1999: 278-282
1997
5	EE	Mehrdad Nourani, Joan Carletta, Christos A. Papachristou: A Scheme for Integrated Controller-Datapath Fault Testing. DAC 1997: 546-551
4	EE	Joan Carletta, Christos A. Papachristou: Behavioral Testability Insertion for Datapath/Controller Circuits. J. Electronic Testing 11(1): 9-28 (1997)
1995
3	EE	Joan Carletta, Christos A. Papachristou: Testability analysis and insertion for RTL circuits based on pseudorandom BIST. ICCD 1995: 162-167
2		Christos A. Papachristou, Joan Carletta: Test Synthesis in the Behavioral Domain. ITC 1995: 693-702
1	EE	Joan Carletta, Christos A. Papachristou: Structural constraints for circular self-test paths. VTS 1995: 486-491

Coauthor Index

1	Sankar Barua	[15] [16]
2	Amy E. Bell	[15] [16] [17] [18] [19]
3	Hima B. Damecharla	[18] [19]
4	Zhengwei Fang	[13] [14]
5	Firas Hassan	[20] [21] [22]
6	Kishore A. Kotteri	[15] [16] [17]
7	Frederick W. Krach	[13] [14]
8	Mehrdad Nourani	[5] [6] [9] [10] [11]
9	Christos A. Papachristou	[1] [2] [3] [4] [5] [6] [9] [10] [11]
10	M. D. Rayman	[12]
11	Kamal K. Varma	[19]
12	Krishnaraj Varma	[18]
13	Robert J. Veillette	[13] [14]
14	John T. Welch	[7]
15	Elie Yarack	[8]

Colors in the list of coauthors