| 2006 |
|---|
| 10 | EE | Shishpal Rawat,
Raul Camposano,
A. Kahng,
Joseph Sawicki,
Mike Gianfagna,
Naeem Zafar,
A. Sharan:
DFM: where's the proof of value?
DAC 2006: 1061-1062 |
| 2004 |
|---|
| 9 | EE | Shishpal Rawat,
William H. Joyner Jr.,
John A. Darringer,
Daniel Gajski,
Pat O. Pistilli,
Hugo De Man,
Carl Harris,
James Solomon:
Were the good old days all that good?: EDA then and now.
DAC 2004: 543 |
| 2003 |
|---|
| 8 | EE | Rajesh K. Gupta,
Shishpal Rawat,
Sandeep K. Shukla,
Brian Bailey,
Daniel K. Beece,
Masahiro Fujita,
Carl Pixley,
John O'Leary,
Fabio Somenzi:
Formal verification - prove it or pitch it.
DAC 2003: 710-711 |
| 7 | EE | Robert Dahlberg,
Shishpal Rawat,
Jen Bernier,
Gina Gloski,
Aurangzeb Khan,
Kaushik Patel,
Paul Ruddy,
Naveed A. Sherwani,
Ronnie Vasishta:
COT - customer owned trouble.
DAC 2003: 91-92 |
| 6 | EE | Shishpal Rawat,
Hans-Joachim Wunderlich:
Introduction.
ACM Trans. Design Autom. Electr. Syst. 8(4): 397-398 (2003) |
| 2002 |
|---|
| 5 | EE | David L. Dill,
Nate James,
Shishpal Rawat,
Gérard Berry,
Limor Fix,
Harry Foster,
Rajeev K. Ranjan,
Gunnar Stålmarck,
Curt Widdoes:
Formal verification methods: getting around the brick wall.
DAC 2002: 576-577 |
| 2001 |
|---|
| 4 | EE | Rajesh K. Gupta,
Shishpal Rawat,
Ingrid Verbauwhede,
Gérard Berry,
Ramesh Chandra,
Daniel Gajski,
Kris Konigsfeld,
Patrick Schaumont:
Panel: The Next HDL: If C++ is the Answer, What was the Question?
DAC 2001: 71-72 |
| 2000 |
|---|
| 3 | EE | T. Karn,
Shishpal Rawat,
Desmond Kirkpatrick,
Rabindra K. Roy,
Greg Spirakis,
Naveed A. Sherwani,
Craig Peterson:
EDA challenges facing future microprocessor design.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(12): 1498-1506 (2000) |
| 1991 |
|---|
| 2 | | Paul G. Ryan,
Shishpal Rawat,
W. Kent Fuchs:
Two-Stage Fault Location.
ITC 1991: 963-968 |
| 1986 |
|---|
| 1 | | Tin-Fook Ngai,
Mary Jane Irwin,
Shishpal Rawat:
Regular Area-Time Efficient Carry-Lookahead Adders.
J. Parallel Distrib. Comput. 3(1): 92-105 (1986) |
