| 2008 |
|---|
| 29 | EE | Fred Tzeng,
Amin Jahanian,
Payam Heydari:
A Universal Code-Modulated Path-Sharing Multi-Antenna Receiver.
WCNC 2008: 616-621 |
| 2007 |
|---|
| 28 | EE | Jeffrey Johnson,
Vipul Jain,
Payam Heydari:
A Nonlinear Model for Phase Noise and Jitter in LC Oscillators.
ISCAS 2007: 3095-3098 |
| 2006 |
|---|
| 27 | EE | Fred Tzeng,
Payam Heydari:
A novel millimeter-wave multi-order LC oscillator.
ISCAS 2006 |
| 26 | EE | Amin Shameli,
Payam Heydari:
A novel power optimization technique for ultra-low power RFICs.
ISLPED 2006: 274-279 |
| 2005 |
|---|
| 25 | EE | Amin Q. Safarian,
Payam Heydari:
A study of high-frequency regenerative frequency dividers.
ISCAS (3) 2005: 2695-2698 |
| 24 | EE | Payam Heydari:
Design Considerations for Low-Power Ultra Wideband Receivers.
ISQED 2005: 668-673 |
| 23 | EE | Amin Q. Safarian,
Ahmad Yazdi,
Payam Heydari:
Design and analysis of an ultrawide-band distributed CMOS mixer.
IEEE Trans. VLSI Syst. 13(5): 618-629 (2005) |
| 22 | EE | Payam Heydari,
Massoud Pedram:
Capacitive coupling noise in high-speed VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 478-488 (2005) |
| 2004 |
|---|
| 21 | EE | Payam Heydari:
High-frequency noise in RF active CMOS mixers.
ASP-DAC 2004: 57-60 |
| 20 | EE | Ahmad Yazdi,
Payam Heydari:
A novel non-uniform distributed amplifier.
ISCAS (1) 2004: 613-616 |
| 19 | EE | Amin Q. Safarian,
Payam Heydari:
Design and analysis of a distributed regenerative frequency divider using distributed mixer.
ISCAS (1) 2004: 992-995 |
| 18 | | Ravindran Mohanavelu,
Payam Heydari:
A novel ultra high-speed flip-flop-based frequency divider.
ISCAS (4) 2004: 169-172 |
| 17 | EE | Ahmad Yazdi,
Payam Heydari:
The Design and Analysis of Non-Uniform Down-Sized Differential Distributed Amplifiers.
ISQED 2004: 528-533 |
| 16 | EE | Payam Heydari,
Ravindran Mohanavelu:
Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.
IEEE Trans. VLSI Syst. 12(10): 1081-1093 (2004) |
| 2003 |
|---|
| 15 | EE | Payam Heydari:
Design issues in low-voltage high-speed current-mode logic buffers.
ACM Great Lakes Symposium on VLSI 2003: 21-26 |
| 14 | EE | Payam Heydari:
Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators.
DAC 2003: 532-537 |
| 13 | EE | Payam Heydari,
Ravindran Mohanavelu:
Design of ultra high-speed CMOS CML buffers and latches.
ISCAS (2) 2003: 208-211 |
| 12 | EE | Payam Heydari,
Ying Zhang:
A novel high frequency, high-efficiency, differential class-E power amplifier in 0.18mum CMOS.
ISLPED 2003: 455-458 |
| 11 | EE | Soroush Abbaspour,
Massoud Pedram,
Payam Heydari:
Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers.
ISQED 2003: 261-266 |
| 10 | EE | Payam Heydari:
Design and Analysis of Low-Voltage Current-Mode Logic Buffers.
ISQED 2003: 293-298 |
| 9 | EE | Payam Heydari,
Massoud Pedram:
Ground bounce in digital VLSI circuits.
IEEE Trans. VLSI Syst. 11(2): 180-193 (2003) |
| 2002 |
|---|
| 8 | EE | Payam Heydari:
Energy dissipation modeling of lossy transmission lines driven by CMOS inverters.
ISCAS (4) 2002: 309-312 |
| 7 | EE | Payam Heydari,
Massoud Pedram:
Interconnect Energy Dissipation in High-Speed ULSI Circuits.
VLSI Design 2002: 132- |
| 2001 |
|---|
| 6 | EE | Payam Heydari,
Massoud Pedram:
Balanced truncation with spectral shaping for RLC interconnects.
ASP-DAC 2001: 203-208 |
| 5 | EE | Payam Heydari,
Massoud Pedram:
Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation.
ICCAD 2001: 586-591 |
| 4 | | Payam Heydari,
Massoud Pedram:
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits.
ICCD 2001: 104-109 |
| 3 | | Payam Heydari,
Massoud Pedram:
Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective.
ICCD 2001: 209-213 |
| 2000 |
|---|
| 2 | EE | Payam Heydari,
Massoud Pedram:
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits.
ICCD 2000: 121-126 |
| 1998 |
|---|
| 1 | EE | Payam Heydari,
Massoud Pedram:
Calculation of ramp response of lossy transmission lines using two-port network functions.
ISPD 1998: 152-157 |
