2008 | ||
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38 | EE | Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu: A General Failure Candidate Ranking Framework for Silicon Debug. VTS 2008: 352-358 |
2006 | ||
37 | EE | Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang: Visibility enhancement for silicon debug. DAC 2006: 13-18 |
36 | EE | Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu: Diagnosing Silicon Failures Based on Functional Test Patterns. MTV 2006: 94-98 |
2003 | ||
35 | EE | Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai: Advanced techniques for RTL debugging. DAC 2003: 362-367 |
2002 | ||
34 | EE | Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai: Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. ACM Trans. Design Autom. Electr. Syst. 7(1): 217-230 (2002) |
2000 | ||
33 | EE | Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai: Timing optimization on routed designs with incremental placementand routing characterization. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 188-196 (2000) |
1999 | ||
32 | EE | Enoch Hwang, Frank Vahid, Yu-Chin Hsu: FSMD Functional Partitioning for Low Power. DATE 1999: 22-27 |
31 | EE | Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai: Post-routing timing optimization with routing characterization. ISPD 1999: 30-35 |
1998 | ||
30 | EE | Frank Vahid, Thuy Dm Le, Yu-Chin Hsu: Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance. ACM Trans. Design Autom. Electr. Syst. 3(2): 181-208 (1998) |
29 | EE | Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee: Eliminating false loops caused by sharing in control path. ACM Trans. Design Autom. Electr. Syst. 3(3): 487-495 (1998) |
1996 | ||
28 | EE | Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita: Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. DAC 1996: 585-590 |
27 | EE | Frank Vahid, Thuy Dm Le, Yu-Chin Hsu: A Comparison of Functional and Structural Partitioning. ISSS 1996: 121-126 |
26 | EE | Alan Su, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee: Eliminating False Loops Caused by Sharing in Control Path. ISSS 1996: 39-44 |
1995 | ||
25 | EE | Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang: Synthesis of false loop free circuits. ASP-DAC 1995 |
1994 | ||
24 | How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang: Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC 1994: 425-429 | |
23 | EE | Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King: MULTIPAR: behavioral partition for synthesizing multiprocessor architectures. IEEE Trans. VLSI Syst. 2(1): 21-32 (1994) |
22 | EE | Ting-Hai Chao, Yu-Chin Hsu: Rectilinear Steiner tree construction by local and global refinement. IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 303-309 (1994) |
1993 | ||
21 | EE | Yuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee: High throughput pipelined data path synthesis by conserving the regularity of nested loops. ICCAD 1993: 450-453 |
20 | EE | Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu: An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 410-424 (1993) |
19 | EE | Cheng-Tsung Hwang, Yu-Chin Hsu: Zone scheduling. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 926-934 (1993) |
18 | EE | Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: PLS: a scheduler for pipeline synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1279-1286 (1993) |
1992 | ||
17 | EE | Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho: Zero Skew Clock Net Routing. DAC 1992: 518-523 |
16 | EE | Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang: A new approach to schedule operations across nested-ifs and nested-loops. MICRO 1992: 268-271 |
15 | EE | Fur-Shing Tsai, Yu-Chin Hsu: STAR: An automatic data path allocator. IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1053-1064 (1992) |
1991 | ||
14 | EE | Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu: An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. DAC 1991: 481-486 |
13 | EE | Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: Scheduling for Functional Pipelining and Loop Winding. DAC 1991: 764-769 |
12 | Shi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu: Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits. ICCAD 1991: 38-41 | |
11 | Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao: Combining Logic Minimization and Folding for PLA's. IEEE Trans. Computers 40(6): 706-713 (1991) | |
10 | EE | Cheng-Tsung Hwang, Jiahn-Humg Lee, Yu-Chin Hsu: A formal approach to the scheduling problem in high level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 464-475 (1991) |
9 | EE | Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu: LiB: a CMOS cell compiler. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 994-1005 (1991) |
1990 | ||
8 | EE | Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu: LiB: A Cell Layout Generator. DAC 1990: 474-479 |
7 | EE | Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu: Data Path Allocation Based on Bipartite Weighted Matching. DAC 1990: 499-504 |
6 | EE | Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: Optimum and Heuristic Data Path Scheduling Under Resource Constraints. DAC 1990: 65-70 |
5 | Fur-Shing Tsai, Yu-Chin Hsu: Data Path Construction and Refinement. ICCAD 1990: 308-311 | |
4 | Ting-Hai Chao, Yu-Chin Hsu: Rectilinear Steiner Tree Construction by Local and Global Refinement. ICCAD 1990: 432-435 | |
3 | EE | Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai: Hybrid routing. IEEE Trans. on CAD of Integrated Circuits and Systems 9(2): 151-157 (1990) |
2 | EE | Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu: A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 781-786 (1990) |
1989 | ||
1 | EE | Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai: SILK: a simulated evolution router. IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1108-1114 (1989) |