| 2007 |
|---|
| 10 | EE | John Moondanos:
From Error to Error: Logic Debugging in the Many-Core Era.
Electr. Notes Theor. Comput. Sci. 174(4): 3-7 (2007) |
| 2006 |
|---|
| 9 | EE | Sung-Jui (Song-Ra) Pan,
Kwang-Ting Cheng,
John Moondanos,
Ziyad Hanna:
Generation of shorter sequences for high resolution error diagnosis using sequential SAT.
ASP-DAC 2006: 25-29 |
| 2005 |
|---|
| 8 | EE | Abhijit Davare,
Qi Zhu,
John Moondanos,
Alberto L. Sangiovanni-Vincentelli:
JPEG Encoding on the Intel MXP5800: A Platform-Based Design Case Study.
ESTImedia 2005: 89-94 |
| 2004 |
|---|
| 7 | EE | Maher N. Mneimneh,
Karem A. Sakallah,
John Moondanos:
Preserving synchronizing sequences of sequential circuits after retiming.
ASP-DAC 2004: 579-584 |
| 6 | EE | Feng Lu,
Li-C. Wang,
Kwang-Ting (Tim) Cheng,
John Moondanos,
Ziyad Hanna:
A Signal Correlation Guided Circuit-SAT Solver.
J. UCS 10(12): 1629-1654 (2004) |
| 2003 |
|---|
| 5 | EE | Feng Lu,
Li-C. Wang,
Kwang-Ting Cheng,
John Moondanos,
Ziyad Hanna:
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.
DAC 2003: 436-441 |
| 2001 |
|---|
| 4 | EE | John Moondanos,
Carl-Johan H. Seger,
Ziyad Hanna,
Daher Kaiss:
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination.
CAV 2001: 131-143 |
| 1997 |
|---|
| 3 | EE | Yatin Vasant Hoskote,
Jacob A. Abraham,
Donald S. Fussell,
John Moondanos:
Automatic verification of implementations of large circuits against HDL specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 217-228 (1997) |
| 1994 |
|---|
| 2 | | Yatin Vasant Hoskote,
John Moondanos,
Jacob A. Abraham,
Donald S. Fussell:
Verification of Circuits Described in VHDL through Extraction of Design Intent.
VLSI Design 1994: 417-420 |
| 1992 |
|---|
| 1 | | John Moondanos,
Jacob A. Abraham:
Sequential Redundancy Identification Using Verification Techniques.
ITC 1992: 197-205 |
