| 2008 |
|---|
| 6 | EE | Kaijian Shi:
Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities.
ICCD 2008: 170-175 |
| 5 | EE | Kaijian Shi,
Zhian Lin,
Yi-Min Jiang,
Lin Yuan:
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs.
JCP 3(3): 6-13 (2008) |
| 2007 |
|---|
| 4 | EE | Kaijian Shi,
Zhian Lin,
Yi-Min Jiang:
A Power Network Synthesis Method for Industrial Power Gating Designs.
ISQED 2007: 362-367 |
| 2006 |
|---|
| 3 | EE | Kaijian Shi,
David Howard:
Challenges in sleep transistor design and implementation in low-power designs.
DAC 2006: 113-116 |
| 2005 |
|---|
| 2 | EE | Thi Nguyen,
Kaijian Shi:
Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs.
ASAP 2005: 204-212 |
| 2003 |
|---|
| 1 | EE | Kaijian Shi,
Graig Godwin:
Hybrid hierarchical timing closure methodology for a high performance and low power DSP.
DAC 2003: 850-855 |
