2008 |
17 | | Victor V. Zhirnov,
Greg Leeming,
Kosmas Galatsis,
Ralph K. Cavin III:
The Viability of Cellular Automata Architectures for General Purpose Computing.
ERSA 2008: 321-333 |
16 | EE | Victor V. Zhirnov,
Ralph K. Cavin III,
Greg Leeming,
Kosmas Galatsis:
An Assessment of Integrated Digital Cellular Automata Architectures.
IEEE Computer 41(1): 38-44 (2008) |
2004 |
15 | EE | Rizwan Bashirullah,
Wentai Liu,
Ralph K. Cavin III,
Dale Edwards:
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability.
IEEE Trans. VLSI Syst. 12(8): 876-880 (2004) |
2003 |
14 | EE | Rizwan Bashirullah,
Wentai Liu,
Ralph K. Cavin III:
Low-power design methodology for an on-chip bus with adaptive bandwidth capability.
DAC 2003: 628-633 |
13 | EE | Rizwan Bashirullah,
Wentai Liu,
Ralph K. Cavin III:
Accurate delay model and experimental verification for current/voltage mode on-chip interconnects.
ISCAS (5) 2003: 169-172 |
12 | EE | Rizwan Bashirullah,
Wentai Liu,
Ralph K. Cavin III:
Current-mode signaling in deep submicrometer global interconnects.
IEEE Trans. VLSI Syst. 11(3): 406-417 (2003) |
2000 |
11 | EE | Hong-Yean Hsieh,
Wentai Liu,
Ralph K. Cavin III:
Integrated parametric timing optimization of digital systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 482-489 (2000) |
1997 |
10 | EE | Hong-Yean Hsieh,
Wentai Liu,
Paul D. Franzon,
Ralph K. Cavin III:
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.
VLSI Signal Processing 16(2-3): 131-147 (1997) |
1995 |
9 | EE | Gary C. Moyer,
Mark Clements,
Wentai Liu,
Toby Schaffer,
Ralph K. Cavin III:
A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.
ARVLSI 1995: 131-149 |
8 | EE | Hong-Yean Hsieh,
Wentai Liu,
Ralph K. Cavin III,
C. Thomas Gray:
Concurrent timing optimization of latch-based digital systems.
ICCD 1995: 680- |
7 | | Gary C. Moyer,
Mark Clements,
Wentai Liu,
Toby Schaffer,
Ralph K. Cavin III:
High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique.
ISCAS 1995: 405-408 |
1994 |
6 | EE | C. Thomas Gray,
Wentai Liu,
Ralph K. Cavin III:
Timing constraints for wave-pipelined systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 987-1004 (1994) |
1991 |
5 | | C. Thomas Gray,
Thomas A. Hughes,
Sanjay Arora,
Wentai Liu,
Ralph K. Cavin III:
Theoretical and Practical Issues in CMOS Wave Pipelining.
VLSI 1991: 397-409 |
1989 |
4 | | Wentai Liu,
Thomas H. Hildebrandt,
Ralph K. Cavin III:
Hamiltonian Cycles in the Shuffle-Exchange Network.
IEEE Trans. Computers 38(5): 745-750 (1989) |
1988 |
3 | | Wentai Liu,
Tong-Fei Yeh,
William E. Batchelor,
Ralph K. Cavin III:
Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions.
ISCA 1988: 167-174 |
1984 |
2 | | Robert M. Burger,
Ralph K. Cavin III,
William C. Holton,
Larry W. Sumney:
The Impact of ICs on Computer Technology.
IEEE Computer 17(10): 88-95 (1984) |
1982 |
1 | | Stephen K. Jones,
Ralph K. Cavin III,
William M. Reed:
Analysis of error-gradient adaptive linear estimators for a class of stationary dependent processes.
IEEE Transactions on Information Theory 28(2): 318-329 (1982) |