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David Yu-Liang Wu
List of publications from the DBLP Bibliography Server - FAQ
2008 | ||
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47 | EE | Hongbing Fan, Christian Hundt, Yu-Liang Wu, Jason Ernst: Algorithms and Implementation for Interconnection Graph Problem. COCOA 2008: 201-210 |
46 | EE | Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: Material Fatigue and Reliability of MEMS Accelerometers. DFT 2008: 314-322 |
45 | Wai-Chung Tang, Catherine L. Zhou, Yu-Liang Wu: A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability. ERSA 2008: 116-121 | |
44 | Hongbing Fan, Yu-Liang Wu: Interconnection Graph Problem. FCS 2008: 51-55 | |
43 | EE | Hongbing Fan, Jason Ernst, Yu-Liang Wu: Customized Reconfigurable Interconnection Networks for multiple application SOCS. FPL 2008: 491-494 |
42 | Jian-Liang Wu, Yu-Liang Wu: The Vertex Linear Arboricity of Claw-Free Graphs with Small Degree. Ars Comb. 86: (2008) | |
2007 | ||
41 | EE | Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu: How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs. DAC 2007: 922-927 |
40 | EE | Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu: Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring. ISCAS 2007: 1049-1052 |
39 | EE | Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung: The exact channel density and compound design for generic universal switch blocks. ACM Trans. Design Autom. Electr. Syst. 12(2): (2007) |
2006 | ||
38 | EE | Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: Reliability Analysis of Self-Repairable MEMS Accelerometer. DFT 2006: 236-244 |
37 | EE | Hongbing Fan, Yu-Liang Wu, Ray Chak-Chung Cheung, Jiping Liu: Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes. IEEE Trans. Computers 55(4): 373-384 (2006) |
2005 | ||
36 | EE | Hongbing Fan, Yu-Liang Wu: Crossbar based design schemes for switch boxes and programmable interconnection networks. ASP-DAC 2005: 910-915 |
35 | EE | Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: Design and Analysis of Self-Repairable MEMS Accelerometer. DFT 2005: 21-32 |
34 | EE | Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang: FPGA technology mapping optimization by rewiring algorithms. ISCAS (6) 2005: 5653-5656 |
33 | EE | Yu-Liang Wu, Chi-Kong Chan: On Improved Least Flexibility First Heuristics Superior for Packing and Stock Cutting Problems. SAGA 2005: 70-81 |
2004 | ||
32 | EE | Dong Xiang, Ming-Jing Chen, Kaiwei Li, Yu-Liang Wu: Scan-Based BIST Using an Improved Scan Forest Architecture. Asian Test Symposium 2004: 88-93 |
31 | EE | Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu: On Optimal Irregular Switch Box Designs. FPL 2004: 189-199 |
30 | EE | Yuen-Ting Wu, Yu-Liang Wu: A Less Flexibility First Based Algorithm for the Container Loading Problem. OR 2004: 368-376 |
29 | EE | Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. VTS 2004: 148-153 |
2003 | ||
28 | EE | Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu: A cost-effective scan architecture for scan testing with non-scan test power and test application cost. DAC 2003: 744-747 |
27 | EE | Hongbing Fan, Jiping Liu, Yu-Liang Wu: General Models and a Reduction Design Technique for FPGA Switch Box Designs. IEEE Trans. Computers 52(1): 21-30 (2003) |
26 | EE | Yu-Liang Wu, Chak-Chung Cheung, David Ihsin Cheng, Hongbing Fan: Further improve circuit partitioning using GBAW logic perturbation techniques. IEEE Trans. VLSI Syst. 11(3): 451-460 (2003) |
25 | EE | Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung: On optimal hyperuniversal and rearrangeable switch box designs. IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1637-1649 (2003) |
2002 | ||
24 | EE | Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung: On Optimum Designs of Universal Switch Blocks. FPL 2002: 142-151 |
23 | EE | Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong: Reduction design for generic universal switch blocks. ACM Trans. Design Autom. Electr. Syst. 7(4): 526-546 (2002) |
22 | EE | Yu-Liang Wu, Wenqi Huang, Siu-Chung Lau, C. K. Wong, Gilbert H. Young: An effective quasi-human based heuristic for solving the rectangle packing problem. European Journal of Operational Research 141(2): 341-358 (2002) |
21 | EE | Hongbing Fan, Yu-Liang Wu, Yao-Wen Chang: Comment on Generic Universal Switch Blocks. IEEE Trans. Computers 51(1): 93-96 (2002) |
2001 | ||
20 | EE | Chin Ngai Sze, Yu-Liang Wu: Improved alternative wiring scheme applying dominator relationship. ASP-DAC 2001: 473-478 |
19 | EE | Hongbing Fan, Jiping Liu, Yu-Liang Wu: Combinatorial routing analysis and design of universal switch blocks. ASP-DAC 2001: 641-644 |
18 | EE | Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung: On Optimum Switch Box Designs for 2-D FPGAs. DAC 2001: 203-208 |
17 | EE | Chak-Chung Cheung, Yu-Liang Wu, David Ihsin Cheng: Further improve circuit partitioning using GBAW logic perturbation techniques. DATE 2001: 233-239 |
16 | EE | Hongbing Fan, Yu-Liang Wu, C. K. Wong: On Fixed Edges and Edge-Reconstruction of Series-Parallel Networks. Graphs and Combinatorics 17(2): 213-225 (2001) |
2000 | ||
15 | EE | Wangning Long, Yu-Liang Wu, Jinian Bian: IBAW: an implication-tree based alternative-wiring logic transformation algorithm. ASP-DAC 2000: 415-422 |
14 | EE | Yu-Liang Wu, Xiao-Long Yuan, David Ihsin Cheng: Circuit partitioning with coupled logic restructuring techniques. ASP-DAC 2000: 655-660 |
13 | Hongbing Fan, Jiping Liu, Yu-Liang Wu: General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs. ICCAD 2000: 93-98 | |
12 | EE | Yu-Liang Wu, Wangning Long, Hongbing Fan: A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. VLSI Design 2000: 268-273 |
11 | EE | Yu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong: OBDD Minimization Based on Two-Level Representation of Boolean Functions. IEEE Trans. Computers 49(12): 1371-1379 (2000) |
1999 | ||
10 | EE | Jin Ding, Yu-Liang Wu: On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults. ASP-DAC 1999: 311-314 |
1998 | ||
9 | Jiaofeng Pan, Yu-Liang Wu, C. K. Wong: On the Optimal Sub-routing Structures of 2-D FPGA Greedy Routing Architectures. ASP-DAC 1998: 535-540 | |
8 | EE | Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu: A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. ITC 1998: 322-330 |
7 | EE | Jiaofeng Pan, Yu-Liang Wu, C. K. Wong, Guiying Yan: On the optimal four-way switch box routing structures of FPGA greedy routing architectures1. Integration 25(2): 137-159 (1998) |
1997 | ||
6 | EE | Yu-Liang Wu, Malgorzata Marek-Sadowska: Routing for array-type FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 506-518 (1997) |
1996 | ||
5 | EE | Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska: Graph based analysis of 2-D FPGA routing. IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 33-44 (1996) |
1995 | ||
4 | EE | Yu-Liang Wu, Malgorzata Marek-Sadowska: Routing on regular segmented 2-D FPGAs. ASP-DAC 1995 |
3 | EE | Yu-Liang Wu, Malgorzata Marek-Sadowska: Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. DAC 1995: 568-573 |
1994 | ||
2 | Yu-Liang Wu, Malgorzata Marek-Sadowska: An Efficient Router for 2-D Field Programmable Gate Arrays. EDAC-ETC-EUROASIC 1994: 412-416 | |
1 | EE | Yu-Liang Wu, Douglas Chang: On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution. ICCAD 1994: 362-366 |