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ASP-DAC 2006: Yokohama, Japan

Fumiyasu Hirose (Ed.): Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006. IEEE 2006, ISBN 0-7803-9451-8 BibTeX

Keynote address I

Keynote address II

Keynote address III

Formal methods for coverage and scalable verification

Interconnect for high-end SoC

Timing analysis and optimization

University design contest

Software techniques for efficient SoC design

Application examples with leading edge design methodology


Special session: electrothermal design of nanoscale integrated circuits

Logic Synthesis

Future technical directions for design automation

Routing and interconnect optimization

Special session: flash memory in embedded systems

Resolving timing issues: design and test

Leading edge design methodology for SoCs and SiPs

Advanced circuit simulation

Special session: open access overview

Advances in simulation technologies

Scheduling for embedded systems

High frequency interconnect effects in nanometer technology

Designers' forum: low power design

Power optimization of large-scale circuits

Advanced memory and processor architectures for MPSoC

New routing techniques

Minimization of test cost and power

Substrate coupling and analog synthesis

Statistical and yield analysis

Special session: H.264/AVC design challenges and solutions


Memory optimization for embedded systems

Inductive issues in power grids and packages

Designers' forum: "cell" processor

High-level synthesis

Modeling, compilation and optimization of embedded architectures

Statistical design

Copyright © Sat May 16 22:58:46 2009 by Michael Ley (ley@uni-trier.de)