| 2007 |
|---|
| 44 | EE | Pi-Chen Hsiao,
Tay-Jyi Lin,
Chih-Wei Liu,
Chein-Wei Jen:
Latency-Tolerant Virtual Cluster Architecture for VLIW DSP.
ISCAS 2007: 3506-3509 |
| 2006 |
|---|
| 43 | EE | Shih-Hao Ou,
Tay-Jyi Lin,
Chao-Wei Huang,
Yu-Ting Kuo,
Chie-Min Chao,
Chih-Wei Liu,
Chein-Wei Jen:
A 52mW 1200MIPS compact DSP for multi-core media SoC.
ASP-DAC 2006: 118-119 |
| 42 | EE | David Chih-Wei Chang,
I-Tao Liao,
Jenq Kuen Lee,
Wen-Feng Chen,
Shau-Yin Tseng,
Chein-Wei Jen:
PAC DSP Core and Application Processors.
ICME 2006: 289-292 |
| 41 | EE | Yu-Ting Kuo,
Tay-Jyi Lin,
Yi Cho,
Chih-Wei Liu,
Chein-Wei Jen:
Programmable FIR filter with adder-based computing engine.
ISCAS 2006 |
| 2005 |
|---|
| 40 | EE | Tay-Jyi Lin,
Chie-Min Chao,
Chia-Hsien Liu,
Pi-Chen Hsiao,
Shin-Kai Chen,
Li-Chun Lin,
Chih-Wei Liu,
Chein-Wei Jen:
A unified processor architecture for RISC & VLIW DSP.
ACM Great Lakes Symposium on VLSI 2005: 50-55 |
| 39 | EE | Yu-Ting Kuo,
Tay-Jyi Lin,
Chih-Wei Liu,
Chein-Wei Jen:
Architecture for area-efficient 2-D transform in H.264/AVC.
ICME 2005: 1126-1129 |
| 38 | EE | Wei-Sheng Huang,
Tay-Jyi Lin,
Shih-Hao Ou,
Chih-Wei Liu,
Chein-Wei Jen:
Pipelining technique for energy-aware datapaths.
ISCAS (2) 2005: 1218-1221 |
| 37 | EE | Chia-Hsien Liu,
Tay-Jyi Lin,
Chie-Min Chao,
Pi-Chen Hsiao,
Li-Chun Lin,
Shin-Kai Chen,
Chao-Wei Huang,
Chih-Wei Liu,
Chein-Wei Jen:
Hierarchical instruction encoding for VLIW digital signal processors.
ISCAS (4) 2005: 3503-3506 |
| 36 | EE | Kun-Bin Lee,
Jih-Yiing Lin,
Chein-Wei Jen:
A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding.
IEEE Trans. Circuits Syst. Video Techn. 15(2): 283-295 (2005) |
| 35 | EE | Hun-Chen Chen,
Jiun-In Guo,
Tian-Sheuan Chang,
Chein-Wei Jen:
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform.
IEEE Trans. Circuits Syst. Video Techn. 15(3): 445-453 (2005) |
| 34 | EE | Kun-Bin Lee,
Tzu-Chieh Lin,
Chein-Wei Jen:
An Efficient Quality-Aware Memory Controller for Multimedia Platform SoC.
IEEE Trans. Circuits Syst. Video Techn. 15(5): 620-633 (2005) |
| 33 | EE | Hun-Chen Chen,
Tian-Sheuan Chang,
Jiun-In Guo,
Chein-Wei Jen:
The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning.
IEICE Transactions 88-C(5): 1061-1069 (2005) |
| 2004 |
|---|
| 32 | EE | Tay-Jyi Lin,
Hung-Yueh Lin,
Chie-Min Chao,
Chih-Wei Liu,
Chein-Wei Jen:
A compact DSP core with static floating-point unit & its microcode generation.
ACM Great Lakes Symposium on VLSI 2004: 57-60 |
| 31 | EE | Kun-Bin Lee,
Nelson Yen-Chung Chang,
Hao-Yun Chin,
Hui-Cheng Hsu,
Chein-Wei Jen:
A bandwidth and memory efficient MPEG-4 shape encoder.
ASP-DAC 2004: 525-526 |
| 30 | | Nelson Yen-Chung Chang,
Kun-Bin Lee,
Chein-Wei Jen:
Trace-path analysis and performance estimation for multimedia application in embedded system.
ISCAS (2) 2004: 129-132 |
| 29 | | Kun-Bin Lee,
Hao-Yun Chin,
Hui-Cheng Hsu,
Chein-Wei Jen:
QME: an efficient subsampling-based block matching algorithm for motion estimation.
ISCAS (2) 2004: 305-308 |
| 28 | | Kun-Bin Lee,
Jih-Yiing Lin,
Chein-Wei Jen:
A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding.
ISCAS (2) 2004: 317-320 |
| 27 | | Kun-Bin Lee,
Hui-Cheng Hsu,
Chein-Wei Jen:
A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization.
ISCAS (2) 2004: 777-780 |
| 26 | | Hung-Yueh Lin,
Tay-Jyi Lin,
Chie-Min Chao,
Yen-Chin Liao,
Chih-Wei Liu,
Chein-Wei Jen:
Static floating-point unit with implicit exponent tracking for embedded DSP.
ISCAS (2) 2004: 821-824 |
| 2003 |
|---|
| 25 | EE | Tay-Jyi Lin,
Chin-Chi Chang,
Chen-Chia Lee,
Chein-Wei Jen:
An Efficient VLIW DSP Architecture for Baseband Processing.
ICCD 2003: 307-312 |
| 24 | EE | Hun-Chen Chen,
Jiun-In Guo,
Chein-Wei Jen:
A memory efficient realization of cyclic convolution and its application to discrete cosine transform.
ISCAS (4) 2003: 33-36 |
| 23 | EE | Tay-Jyi Lin,
Tsung-Hsun Yang,
Chein-Wei Jen:
Area-effective FIR filter design for multiplier-less implementation.
ISCAS (5) 2003: 173-176 |
| 22 | EE | Wen-Chang Yeh,
Chein-Wei Jen:
Generalized Earliest-First Fast Addition Algorithm.
IEEE Trans. Computers 52(10): 1233-1242 (2003) |
| 21 | EE | Yuan-Chung Lee,
Chein-Wei Jen:
Edge-preserving texture filtering for real-time rendering.
The Visual Computer 19(1): 10-22 (2003) |
| 2002 |
|---|
| 20 | EE | Hun-Chen Chen,
Jiun-In Guo,
Chein-Wei Jen:
A new group distributed arithmetic design for the one dimensional discrete Fourier transform.
ISCAS (1) 2002: 421-424 |
| 19 | EE | Tay-Jyi Lin,
Chein-Wei Jen:
CASCADE - configurable and scalable DSP environment.
ISCAS (4) 2002: 870-873 |
| 18 | EE | Yun-Tai Hsiao,
Hung-Der Lin,
Kun-Bin Lee,
Chein-Wei Jen:
High-speed memory-saving architecture for the embedded block coding in JPEG2000.
ISCAS (5) 2002: 133-136 |
| 17 | | Jen-Chieh Tuan,
Tian-Sheuan Chang,
Chein-Wei Jen:
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture.
IEEE Trans. Circuits Syst. Video Techn. 12(1): 61-72 (2002) |
| 16 | EE | Bor-Sung Liang,
Yuan-Chung Lee,
Wen-Chang Yeh,
Chein-Wei Jen:
Index rendering: hardware-efficient architecture for 3-D graphics in multimedia system.
IEEE Transactions on Multimedia 4(3): 343-360 (2002) |
| 2001 |
|---|
| 15 | EE | Yuan-Chung Lee,
Chein-Wei Jen:
Arbitrarily scalable edge-preserving interpolation for 3-D graphics and video resizing.
ISCAS (2) 2001: 317-320 |
| 14 | EE | Tay-Jyi Lin,
Chein-Wei Jen:
An efficient 2-D DWT architecture via resource cycling.
ISCAS (4) 2001: 914-917 |
| 13 | EE | Ilion Yi-Liang Hsiao,
Ding-Hao Wang,
Chein-Wei Jen:
Power modeling and low-power design of content addressable memories.
ISCAS (4) 2001: 926-929 |
| 12 | EE | Yuan-Chung Lee,
Chein-Wei Jen:
Improved quadratic normal vector interpolation for realistic shading.
The Visual Computer 17(6): 337-352 (2001) |
| 2000 |
|---|
| 11 | EE | Yuan-Chung Lee,
Chein-Wei Jen:
On-Line Polygon Refining Using a Low Computation Subdivision Algorithm.
GMP 2000: 209-219 |
| 10 | | Tian-Sheuan Chang,
Chin-Sheng Kung,
Chein-Wei Jen:
A simple processor core design for DCT/IDCT.
IEEE Trans. Circuits Syst. Video Techn. 10(3): 439-447 (2000) |
| 9 | EE | Wen-Chang Yeh,
Chein-Wei Jen:
High-Speed Booth Encoded Parallel Multiplier Design.
IEEE Trans. Computers 49(7): 692-701 (2000) |
| 1998 |
|---|
| 8 | EE | Jen-Chien Tuan,
Chein-Wei Jen:
An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement.
Great Lakes Symposium on VLSI 1998: 152-156 |
| 1996 |
|---|
| 7 | EE | Jinn-Wang Yeh,
Wen-Jiunn Cheng,
Chein-Wei Jen:
VASS - A VLSI array system synthesizer.
VLSI Signal Processing 12(2): 135-158 (1996) |
| 1994 |
|---|
| 6 | | Jiun-In Guo,
Chi-Min Liu,
Chein-Wei Jen:
A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform.
ISCAS 1994: 235-238 |
| 1993 |
|---|
| 5 | | Jiun-In Guo,
Chi-Min Liu,
Chein-Wei Jen:
A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform.
ISCAS 1993: 1571-1574 |
| 4 | | Yu-Sheng Lin,
Jiun-In Guo,
C. Bernard Shung,
Chein-Wei Jen:
A Multi-phase Shared Bus Structure for the Fast Fourier Transform.
ISCAS 1993: 1575-1578 |
| 3 | | Jiann-Jenn Wang,
Chein-Wei Jen:
A High Throughput Systolic Design for QR Algorithm.
ISCAS 1993: 1742-1745 |
| 1992 |
|---|
| 2 | | Chein-Wei Jen,
Ding-Ming Kwai:
Data Flow Representation of Iterative Algorithms for Systolic Arrays.
IEEE Trans. Computers 41(3): 351-355 (1992) |
| 1986 |
|---|
| 1 | | Sun-Yuan Kung,
Chih-Wei Jim Chang,
Chein-Wei Jen:
Real-Time Configuration for Fault-Tolerant VLSI Array Processors.
IEEE Real-Time Systems Symposium 1986: 46-54 |
