Minoru Watanabe

2009
34	EE	Shinya Kubota, Minoru Watanabe: A nine-context programmable optically reconfigurable gate array with semiconductor lasers. ACM Great Lakes Symposium on VLSI 2009: 269-274
33	EE	Mao Nakajima, Minoru Watanabe: Fast Optical Reconfiguration of a Nine-Context DORGA. ARC 2009: 123-132
2008
32	EE	Mao Nakajima, Minoru Watanabe: Dynamic holographic reconfiguration on a four-context ODRGA. ASAP 2008: 173-178
31		Fuminori Kobayashi, Yasuyuki Morikawa, Minoru Watanabe: MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective. ERSA 2008: 222-228
30		Mao Nakajima, Minoru Watanabe: A 770ns Holographic Reconfiguration of a Four-Context DORGA. ERSA 2008: 289-292
29	EE	Mao Nakajima, Daisaku Seto, Minoru Watanabe: A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time. IPDPS 2008: 1-6
28	EE	Kouhi Shinohara, Minoru Watanabe: Defect tolerance of holographic configurations in ORGAs. IPDPS 2008: 1-8
27	EE	Daisaku Seto, Minoru Watanabe: A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory. ISVLSI 2008: 511-514
26	EE	Daisaku Seto, Minoru Watanabe: Analysis of retention time under multi-configuration on a DORGA. SoCC 2008: 131-134
25	EE	Naoki Yamaguchi, Minoru Watanabe: An Optical Reconfiguration System with Four Contexts. VLSI Design 2008: 601-606
24	EE	Minoru Watanabe, Naoki Yamaguchi: An Acceleration and Optimization Method for Optical Reconfiguration. VLSI Design 2008: 607-612
2007
23		Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi: 272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. ERSA 2007: 259-264
22		Minoru Watanabe: Optimization of Reconfiguration-speed Control Bits for an Optically Reconfigurable Gate Array. ERSA 2007: 291-294
21	EE	Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi: A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays. IPDPS 2007: 1-7
20	EE	Minoru Watanabe, Fuminori Kobayashi: Holographic memory reconfigurable VLSI. ISCAS 2007: 401-404
2006
19	EE	Minoru Watanabe, Fuminori Kobayashi: A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ARC 2006: 268-273
18	EE	Minoru Watanabe, Fuminori Kobayashi: A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. ASP-DAC 2006: 108-109
17		Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi: Differential Reconfiguration Architecture suitable for a Holographic Memory. ERSA 2006: 198-206
16		Minoru Watanabe, Fuminori Kobayashi: Logic Synthesis and Place-and-Route Environment for ORGAs. ERSA 2006: 237-238
15		Minoru Watanabe, Fuminori Kobayashi: Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. ERSA 2006: 239-240
14	EE	Minoru Watanabe, Fuminori Kobayashi: A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. FPL 2006: 1-6
13	EE	Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi: An optically differential reconfigurable gate array with a holographic memory. IPDPS 2006
12	EE	Minoru Watanabe, Fuminori Kobayashi: Power consumption advantage of a dynamic optically reconfigurable gate array. IPDPS 2006
2005
11		Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi: Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers. FPT 2005: 287-288
10		Minoru Watanabe, Fuminori Kobayashi: A Zero-Overhead Dynamic Optically Reconfigurable Gate Array. FPT 2005: 297-298
9	EE	Minoru Watanabe, Fuminori Kobayashi: An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. IPDPS 2005
8	EE	Minoru Watanabe, Fuminori Kobayashi: A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. ISCAS (2) 2005: 1214-1217
7	EE	Minoru Watanabe, Fuminori Kobayashi: An Improved Dynamic Optically Reconfigurable Gate Array. ISVLSI 2005: 136-141
6	EE	Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi: Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs. ISVLSI 2005: 274-275
2004
5		Minoru Watanabe, Fuminori Kobayashi: Testing Method for Optical Connections Using Gate Array Structure in ORGAs. ERSA 2004: 299-302
4		Minoru Watanabe, Fuminori Kobayashi: Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors. ERSA 2004: 311
3	EE	Minoru Watanabe, Fuminori Kobayashi: A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. FPL 2004: 261-269
2	EE	Minoru Watanabe, Fuminori Kobayashi: An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. VLSI Design 2004: 735-
2003
1	EE	Minoru Watanabe, Fuminori Kobayashi: An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit. IPDPS 2003: 188

Coauthor Index

1	Fuminori Kobayashi	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [23] [31]
2	Shinya Kubota	[34]
3	Mototsugu Miyano	[6] [11] [13] [17]
4	Rio Miyazaki	[21]
5	Yasuyuki Morikawa	[31]
6	Mao Nakajima	[29] [30] [32] [33]
7	Daisaku Seto	[26] [27] [29]
8	Takenori Shiki	[23]
9	Kouhi Shinohara	[28]
10	Naoki Yamaguchi	[24] [25]

Colors in the list of coauthors