Sudarshan Banerjee

2008
16	EE	Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian: Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies. ACM Trans. Embedded Comput. Syst. 7(2): (2008)
2007
15	EE	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera: Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. DAC 2007: 771-776
14	EE	Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Sudarshan Banerjee: Energy-aware co-processor selection for embedded processors on FPGAs. ICCD 2007: 158-163
13	EE	Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement CoRR abs/0710.4820: (2007)
2006
12	EE	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt: PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. ASP-DAC 2006: 491-496
11	EE	Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian: Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies. CODES+ISSS 2006: 16-21
10	EE	John Augustine, Sudarshan Banerjee, Sandy Irani: Strip packing with precedence constraints and strip packing with release times. SPAA 2006: 180-189
9	EE	Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi: Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. VLSI Design 2006: 651-656
8	EE	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration. IEEE Trans. VLSI Syst. 14(11): 1189-1202 (2006)
7	EE	Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. IEEE Trans. VLSI Syst. 14(7): 754-762 (2006)
2005
6	EE	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. DAC 2005: 335-340
5	EE	Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. DATE 2005: 1246-1251
4	EE	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures. FCCM 2005: 273-274
2004
3	EE	Sudarshan Banerjee, Nikil D. Dutt: FIFO power optimization for on-chip networks. ACM Great Lakes Symposium on VLSI 2004: 187-191
2	EE	Sudarshan Banerjee, Nikil D. Dutt: Efficient search space exploration for HW-SW partitioning. CODES+ISSS 2004: 122-127
1997
1		Sudarshan Banerjee, Sanjeev Saxena: Parallel Algorithms for Finding the Most Vital Edge in Weighted Graphs. J. Parallel Distrib. Comput. 46(1): 101-104 (1997)

Coauthor Index

1	John Augustine	[10]
2	Partha Biswas	[5] [7] [9] [13]
3	Elaheh Bozorgzadeh (Eli Bozorgzadeh)	[4] [6] [8] [12] [14] [15]
4	Nikil D. Dutt (Nikil Dutt)	[2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13] [15] [16]
5	Amir Hossein Gholamipour	[14]
6	Paolo Ienne	[5] [7] [9] [13]
7	Sandy Irani	[10]
8	Minyoung Kim	[11] [16]
9	Juanjo Noguera	[15]
10	Laura Pozzi	[5] [7] [9] [13]
11	Sanjeev Saxena	[1]
12	Nalini Venkatasubramanian	[11] [16]

Colors in the list of coauthors