| 2008 |
|---|
| 63 | EE | Huang-Chih Kuo,
Youn-Long Lin:
An H.264/AVC full-mode intra-frame encoder for 1080HD video.
ICME 2008: 1037-1040 |
| 62 | EE | Cheng-Long Wu,
Chao-Yang Kao,
Youn-Long Lin:
A high performance three-engine architecture for H.264/AVC fractional motion estimation.
ICME 2008: 133-136 |
| 61 | EE | Chao-Yang Kao,
Youn-Long Lin:
A high-performance and memory-efficient architecture for H.264/AVC motion estimation.
ICME 2008: 141-144 |
| 60 | EE | Ping Chao,
Youn-Long Lin:
Reference frame access optimization for ultra high resolution H.264/AVC decoding.
ICME 2008: 1441-1444 |
| 59 | EE | Ping Chao,
Youn-Long Lin:
A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding.
ISCAS 2008: 256-259 |
| 2007 |
|---|
| 58 | EE | Chien-Liang Chen,
Jiing-Yuan Lin,
Youn-Long Lin:
Integration, Verification and Layout of a Complex Multimedia SOC
CoRR abs/0710.4667: (2007) |
| 2006 |
|---|
| 57 | EE | Yu-Chien Kao,
Huang-Chih Kuo,
Yin-Tzu Lin,
Chia-Wen Hou,
Yi-Hsien Li,
Hao-Tin Huang,
Youn-Long Lin:
A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding.
APCCAS 2006: 562-565 |
| 56 | EE | Shen-Yu Shih,
Cheng-Ru Chang,
Youn-Long Lin:
A near optimal deblocking filter for H.264 advanced video coding.
ASP-DAC 2006: 170-175 |
| 55 | EE | Jian-Wen Chen,
Chao-Yang Kao,
Youn-Long Lin:
Introduction to H.264 advanced video coding.
ASP-DAC 2006: 736-741 |
| 54 | EE | Chao-Yang Kao,
Huang-Chih Kuo,
Youn-Long Lin:
High Performance Fractional Motion Estimation and Mode Decision for H.264/AVC.
ICME 2006: 1241-1244 |
| 2005 |
|---|
| 53 | EE | Chien-Liang Chen,
Jiing-Yuan Lin,
Youn-Long Lin:
Integration, Verification and Layout of a Complex Multimedia SOC.
DATE 2005: 1116-1117 |
| 52 | EE | Jian-Wen Chen,
Cheng-Ru Chang,
Youn-Long Lin:
A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC.
ISCAS (5) 2005: 4525-4528 |
| 51 | EE | Sheng-Yu Shih,
Cheng-Ru Chang,
Youn-Long Lin:
An AMBA-compliant deblocking filter IP for H.264/AVC.
ISCAS (5) 2005: 4529-4532 |
| 50 | EE | Kai-Yuan Jan,
Chih-Bin Fan,
An-Chao Kuo,
Wen-Chi Yen,
Youn-Long Lin:
A platform based SOC design methodology and its application in image compression.
IJES 1(1/2): 23-32 (2005) |
| 2004 |
|---|
| 49 | | Tien-Wei Hsieh,
Youn-Long Lin:
A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard.
ESTImedia 2004: 87-90 |
| 2002 |
|---|
| 48 | EE | Chih-Wea Wang,
Jing-Reng Huang,
Yen-Fu Lin,
Kuo-Liang Cheng,
Chih-Tsun Huang,
Cheng-Wen Wu,
Youn-Long Lin:
Test Scheduling of BISTed Memory Cores for SOC.
Asian Test Symposium 2002: 356- |
| 47 | EE | Huan-Shan Hsu,
Jing-Reng Huang,
Kuo-Liang Cheng,
Chih-Wea Wang,
Chih-Tsun Huang,
Cheng-Wen Wu,
Youn-Long Lin:
Test Scheduling and Test Access Architecture Optimization for System-on-Chip.
Asian Test Symposium 2002: 411- |
| 46 | EE | Yih-Chih Chou,
Youn-Long Lin:
Effective enforcement of path-delay constraints inperformance-driven placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 15-22 (2002) |
| 2001 |
|---|
| 45 | EE | Yih-Chih Chou,
Youn-Long Lin:
A 3-step approach for performance-driven whole-chip routing.
ASP-DAC 2001: 187-191 |
| 44 | EE | Yih-Chih Chou,
Youn-Long Lin:
A performance-driven standard-cell placer based on a modified force-directed algorithm.
ISPD 2001: 24-29 |
| 43 | | Hung-Pin Wen,
Chien-Yu Lin,
Youn-Long Lin:
Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design.
ISSS 2001: 233-238 |
| 2000 |
|---|
| 42 | EE | Michael C.-J. Lin,
Youn-Long Lin:
A VLSI implementation of the blowfish encryption/decryption algorithm.
ASP-DAC 2000: 1-2 |
| 41 | EE | Tzu-Chieh Tien,
Youn-Long Lin:
Performance-optimal clustering with retiming for sequential circuits.
ASP-DAC 2000: 409-414 |
| 40 | EE | Hong-Kai Chang,
Youn-Long Lin:
Array allocation taking into account SDRAM characteristics.
ASP-DAC 2000: 497-502 |
| 1999 |
|---|
| 39 | EE | Yun-Yin Lian,
Youn-Long Lin:
Layout-based Logic Decomposition for Timing Optimization.
ASP-DAC 1999: 229-232 |
| 38 | EE | Hsiao-Pin Su,
Allen C.-H. Wu,
Youn-Long Lin:
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning.
DAC 1999: 262-267 |
| 37 | EE | Wei-Kai Cheng,
Youn-Long Lin:
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining.
ACM Trans. Design Autom. Electr. Syst. 4(3): 231-256 (1999) |
| 36 | EE | Hsiao-Pin Su,
Allen C.-H. Wu,
Youn-Long Lin:
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 475-483 (1999) |
| 1998 |
|---|
| 35 | EE | Tzu-Chieh Tien,
Hsiao-Pin Su,
Yu-Wen Tsay,
Yih-Chih Chou,
Youn-Long Lin:
Integrating logic retiming and register placement.
ICCAD 1998: 136-139 |
| 34 | EE | Yih-Chih Chou,
Youn-Long Lin:
A graph-partitioning-based approach for multi-layer constrained via minimization.
ICCAD 1998: 426-429 |
| 33 | EE | Hsiao-Pin Su,
Allen C.-H. Wu,
Youn-Long Lin:
Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy.
ISPD 1998: 12-17 |
| 32 | EE | Wei-Kai Cheng,
Youn-Long Lin:
Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture.
ISSS 1998: 15-22 |
| 1997 |
|---|
| 31 | EE | Yu-Wen Tsay,
Wen-Jong Fang,
Allen C.-H. Wu,
Youn-Long Lin:
Preserving HDL synthesis hierarchy for cell placement.
ISPD 1997: 169-174 |
| 30 | EE | Youn-Long Lin:
Recent developments in high-level synthesis.
ACM Trans. Design Autom. Electr. Syst. 2(1): 2-21 (1997) |
| 29 | EE | Hsiao-Pin Su,
Youn-Long Lin:
A phase assignment method for virtual-wire-based hardware emulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 776-783 (1997) |
| 1996 |
|---|
| 28 | EE | Tsung-Yi Wu,
Youn-Long Lin:
Register minimization beyond sharing among variables.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1583-1587 (1996) |
| 1995 |
|---|
| 27 | EE | Wei-Kai Cheng,
Youn-Long Lin:
A Transformation-Based Approach for Storage Optimization.
DAC 1995: 158-163 |
| 26 | EE | Tsung-Yi Wu,
Youn-Long Lin:
Register Minimization beyond Sharing among Variables.
DAC 1995: 164-169 |
| 25 | EE | Ching-Dong Chen,
Yuh-Sheng Lee,
Allen C.-H. Wu,
Youn-Long Lin:
TRACER-fpga: a router for RAM-based FPGA's.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 371-374 (1995) |
| 24 | EE | Yu-Wen Tsay,
Youn-Long Lin:
A row-based cell placement method that utilizes circuit structural properties.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 393-397 (1995) |
| 23 | EE | Chau-Shen Chen,
Yu-Wen Tsay,
TingTing Hwang,
Allen C.-H. Wu,
Youn-Long Lin:
Combining technology mapping and placement for delay-minimization in FPGA designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1076-1084 (1995) |
| 1994 |
|---|
| 22 | | Tsung-Yi Wu,
Tzu-Chieh Tien,
Allen C.-H. Wu,
Youn-Long Lin:
A Synthesis Method for Mixed Synchronous / Asynchronous Behavior.
EDAC-ETC-EUROASIC 1994: 277-281 |
| 21 | | Kuo-Hua Wang,
Wen-Sing Wang,
TingTing Hwang,
Allen C.-H. Wu,
Youn-Long Lin:
State Assignment for Power and Area Minimization.
ICCD 1994: 250-254 |
| 20 | EE | Yi-Min Jiang,
Tsing-Fa Lee,
TingTing Hwang,
Youn-Long Lin:
Performance-driven interconnection optimization for microarchitecture synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 137-149 (1994) |
| 19 | EE | Tsing-Fa Lee,
Allen C.-H. Wu,
Youn-Long Lin,
Daniel D. Gajski:
A transformation-based method for loop folding.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 439-450 (1994) |
| 1993 |
|---|
| 18 | EE | Chau-Shen Chen,
Yu-Wen Tsay,
TingTing Hwang,
Allen C.-H. Wu,
Youn-Long Lin:
Combining technology mapping and placement for delay-optimization in FPGA designs.
ICCAD 1993: 123-127 |
| 17 | EE | Chi-Yi Hwang,
Yung-Ching Hsieh,
Youn-Long Lin,
Yu-Chin Hsu:
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 410-424 (1993) |
| 16 | EE | Cheng-Tsung Hwang,
Yu-Chin Hsu,
Youn-Long Lin:
PLS: a scheduler for pipeline synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1279-1286 (1993) |
| 1992 |
|---|
| 15 | EE | Tsing-Fa Lee,
Allen C.-H. Wu,
Daniel Gajski,
Youn-Long Lin:
An effective methodology for functional pipelining.
ICCAD 1992: 230-233 |
| 14 | | Yirng-An Chen,
Youn-Long Lin,
Long-Wen Chang:
A Systolic Algorithm for the k-Nearest Neighbors Problem.
IEEE Trans. Computers 41(1): 103-108 (1992) |
| 1991 |
|---|
| 13 | EE | Min-Siang Lin,
Hourng-Wern Perng,
Chi-Yi Hwang,
Youn-Long Lin:
Channel Density Reduction by Routing Over The Cells.
DAC 1991: 120-125 |
| 12 | EE | Chi-Yi Hwang,
Yung-Ching Hsieh,
Youn-Long Lin,
Yu-Chin Hsu:
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation.
DAC 1991: 481-486 |
| 11 | EE | Cheng-Tsung Hwang,
Yu-Chin Hsu,
Youn-Long Lin:
Scheduling for Functional Pipelining and Loop Winding.
DAC 1991: 764-769 |
| 10 | | Yu-Chin Hsu,
Youn-Long Lin,
Hang-Ching Hsieh,
Ting-Hai Chao:
Combining Logic Minimization and Folding for PLA's.
IEEE Trans. Computers 40(6): 706-713 (1991) |
| 9 | EE | Min-Siang Lin,
Houng-Wern Perng,
Chi-Yi Hwang,
Youn-Long Lin:
Channel density reduction by routing over the cells.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1067-1071 (1991) |
| 8 | EE | Yung-Ching Hsieh,
Chi-Yi Hwang,
Youn-Long Lin,
Yu-Chin Hsu:
LiB: a CMOS cell compiler.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 994-1005 (1991) |
| 1990 |
|---|
| 7 | EE | Yung-Ching Hsieh,
Chi-Yi Hwang,
Youn-Long Lin,
Yu-Chin Hsu:
LiB: A Cell Layout Generator.
DAC 1990: 474-479 |
| 6 | EE | Chu-Yi Huang,
Yen-Shen Chen,
Youn-Long Lin,
Yu-Chin Hsu:
Data Path Allocation Based on Bipartite Weighted Matching.
DAC 1990: 499-504 |
| 5 | EE | Cheng-Tsung Hwang,
Yu-Chin Hsu,
Youn-Long Lin:
Optimum and Heuristic Data Path Scheduling Under Resource Constraints.
DAC 1990: 65-70 |
| 4 | EE | Youn-Long Lin,
Yu-Chin Hsu,
Fur-Shing Tsai:
Hybrid routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(2): 151-157 (1990) |
| 3 | EE | Chi-Yi Hwang,
Yung-Chin Hsieh,
Youn-Long Lin,
Yu-Chin Hsu:
A fast transistor-chaining algorithm for CMOS cell layout.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 781-786 (1990) |
| 1989 |
|---|
| 2 | EE | Youn-Long Lin,
Yu-Chin Hsu,
Fur-Shing Tsai:
SILK: a simulated evolution router.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1108-1114 (1989) |
| 1988 |
|---|
| 1 | EE | Youn-Long Lin,
Daniel D. Gajski:
LES: a layout expert system.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(8): 868-876 (1988) |
