| 2008 |
|---|
| 69 | EE | Dongwook Lee,
Sungjoo Yoo,
Kiyoung Choi:
Entry control in network-on-chip for memory power reduction.
ISLPED 2008: 171-176 |
| 68 | EE | V. K. Prasad Arava,
Manhwee Jo,
HyoukJoong Lee,
Kiyoung Choi:
A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines.
ISVLSI 2008: 197-202 |
| 67 | EE | Yongjin Ahn,
Keesung Han,
Ganghee Lee,
Hyunjik Song,
Jun-hee Yoo,
Kiyoung Choi,
Xingguang Feng:
SoCDAL: System-on-chip design AcceLerator.
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 66 | EE | Soonhoi Ha,
Kiyoung Choi,
Taewhan Kim,
Krisztián Flautner,
Sang Lyul Min,
Wang Yi:
Introduction to embedded systems week 2006 special issue.
ACM Trans. Embedded Comput. Syst. 7(2): (2008) |
| 65 | EE | Jong-eun Lee,
Kiyoung Choi,
Nikil Dutt:
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures.
IJES 3(3): 119-127 (2008) |
| 2007 |
|---|
| 64 | | Soonhoi Ha,
Kiyoung Choi,
Nikil D. Dutt,
Jürgen Teich:
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007
ACM 2007 |
| 63 | EE | Imyong Lee,
Dongwook Lee,
Kiyoung Choi:
Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation.
ASAP 2007: 383-390 |
| 62 | EE | Jun-hee Yoo,
Dongwook Lee,
Sungjoo Yoo,
Kiyoung Choi:
Communication Architecture Synthesis of Cascaded Bus Matrix.
ASP-DAC 2007: 171-177 |
| 61 | EE | Ganghee Lee,
Seokhyun Lee,
Yongjin Ahn,
Kiyoung Choi:
Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration.
ICSAMOS 2007: 50-57 |
| 60 | EE | Youngchul Cho,
Nacer-Eddine Zergainoh,
Kiyoung Choi,
Ahmed Amine Jerraya:
Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes.
IEEE International Workshop on Rapid System Prototyping 2007: 195-201 |
| 59 | EE | Youngchul Cho,
Nacer-Eddine Zergainoh,
Ahmed Amine Jerraya,
Kiyoung Choi:
Buffer Size Reduction through Control-Flow Decomposition.
RTCSA 2007: 183-190 |
| 58 | EE | Jong-eun Lee,
Kiyoung Choi,
Nikil D. Dutt:
Instruction set synthesis with efficient instruction encoding for configurable processors.
ACM Trans. Design Autom. Electr. Syst. 12(1): (2007) |
| 57 | EE | Yoonjin Kim,
Mary Kiemb,
Chulsoo Park,
Jinyong Jung,
Kiyoung Choi:
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization
CoRR abs/0710.4704: (2007) |
| 2006 |
|---|
| 56 | | Reinaldo A. Bergamaschi,
Kiyoung Choi:
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006
ACM 2006 |
| 55 | EE | Jun-hee Yoo,
Xingguang Feng,
Kiyoung Choi,
Eui-Young Chung,
Kyu-Myung Choi:
Worst case execution time analysis for synthesized hardware.
ASP-DAC 2006: 905-910 |
| 54 | EE | Minwook Ahn,
Jonghee W. Yoon,
Yunheung Paek,
Yoonjin Kim,
Mary Kiemb,
Kiyoung Choi:
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures.
DATE 2006: 363-368 |
| 53 | EE | Yoonjin Kim,
Ilhyun Park,
Kiyoung Choi,
Yunheung Paek:
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture.
ISLPED 2006: 310-315 |
| 2005 |
|---|
| 52 | EE | Youngchul Cho,
Sungjoo Yoo,
Kiyoung Choi,
Nacer-Eddine Zergainoh,
Ahmed Amine Jerraya:
Scheduler implementation in MP SoC design.
ASP-DAC 2005: 151-156 |
| 51 | EE | Yoonjin Kim,
Mary Kiemb,
Chulsoo Park,
Jinyong Jung,
Kiyoung Choi:
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization.
DATE 2005: 12-17 |
| 50 | EE | Daehong Kim,
Dongwan Shin,
Kiyoung Choi:
Pipelining with common operands for power-efficient linear systems.
IEEE Trans. VLSI Syst. 13(9): 1023-1034 (2005) |
| 2004 |
|---|
| 49 | | Rajiv V. Joshi,
Kiyoung Choi,
Vivek Tiwari,
Kaushik Roy:
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004
ACM 2004 |
| 48 | EE | Mary Kiemb,
Kiyoung Choi:
Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems.
CASES 2004: 230-237 |
| 47 | EE | Whee Kuk Kim,
Kiyoung Choi,
Byung-Ju Yi:
A Mobility Analysis Method of Closed-chain Mechanisms with Over-constraints and Non-holonomic Constraints.
ICRA 2004: 2801-2807 |
| 46 | | Mary Kiemb,
Kiyoung Choi:
Application-specific configuration of multithreaded processor architecture for embedded applications.
ISCAS (2) 2004: 941-944 |
| 2003 |
|---|
| 45 | EE | Jong-eun Lee,
Kiyoung Choi,
Nikil D. Dutt:
Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures.
ASAP 2003: 172-182 |
| 44 | EE | Youngchul Cho,
Ganghee Lee,
Sungjoo Yoo,
Kiyoung Choi,
Nacer-Eddine Zergainoh:
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
DATE 2003: 20132-20137 |
| 43 | EE | Jong-eun Lee,
Kiyoung Choi,
Nikil D. Dutt:
Energy-efficient instruction set synthesis for application-specific processors.
ISLPED 2003: 330-333 |
| 42 | EE | Jong-eun Lee,
Kiyoung Choi,
Nikil D. Dutt:
An algorithm for mapping loops onto coarse-grained reconfigurable architectures.
LCTES 2003: 183-188 |
| 41 | EE | Nikil D. Dutt,
Kiyoung Choi:
Configurable Processors for Embedded Computing.
IEEE Computer 36(1): 120-123 (2003) |
| 40 | EE | Jong-eun Lee,
Kiyoung Choi,
Nikil D. Dutt:
Compilation Approach for Coarse-Grained Reconfigurable Architectures.
IEEE Design & Test of Computers 20(1): 26-33 (2003) |
| 2002 |
|---|
| 39 | EE | Sunghyun Lee,
Sungjoo Yoo,
Kiyoung Choi:
Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model.
CODES 2002: 199-204 |
| 38 | EE | Jong-eun Lee,
Kiyoung Choi,
Nikil Dutt:
Efficient instruction encoding for automatic instruction set design of configurable ASIPs.
ICCAD 2002: 649-654 |
| 37 | EE | Sunghyun Lee,
Kiyoung Choi,
Sungjoo Yoo:
An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model.
ISLPED 2002: 84-87 |
| 2001 |
|---|
| 36 | EE | Jinhwan Jeon,
Daehong Kim,
Dongwan Shin,
Kiyoung Choi:
High-level synthesis under multi-cycle interconnect delay.
ASP-DAC 2001: 662 |
| 35 | EE | Kyoungseok Rha,
Kiyoung Choi:
Area-efficient buffer binding based on a novel two-port FIFO structure.
CODES 2001: 122-127 |
| 34 | EE | Sungtaek Lim,
Jihong Kim,
Kiyoung Choi:
Scheduling-based code size reduction in processors with indirect addressing mode.
CODES 2001: 165-169 |
| 33 | EE | Jinyong Jung,
Sungjoo Yoo,
Kiyoung Choi:
Performance improvement of multi-processor systems cosimulation based on SW analysis.
DATE 2001: 749-753 |
| 32 | EE | Daehong Kim,
Jinyong Jung,
Sunghyun Lee,
Jinhwan Jeon,
Kiyoung Choi:
Behavior-to-Placed RTL Synthesis with Performance-Driven Placement.
ICCAD 2001: 320- |
| 31 | EE | Daehong Kim,
Dongwan Shin,
Kiyoung Choi:
Low power pipelining of linear systems: a common operand centric approach.
ISLPED 2001: 225-230 |
| 30 | EE | Youngsoo Shin,
Soo-Ik Chae,
Kiyoung Choi:
Partial bus-invert coding for power optimization of application-specific systems.
IEEE Trans. VLSI Syst. 9(2): 377-383 (2001) |
| 29 | EE | Youngsoo Shin,
Kiyoung Choi,
Young-Hoon Chang:
Narrow bus encoding for low-power DSP systems.
IEEE Trans. VLSI Syst. 9(5): 656-660 (2001) |
| 28 | EE | Sanghun Park,
Kiyoung Choi:
Performance-driven high-level synthesis with bit-level chaining andclock selection.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 199-212 (2001) |
| 2000 |
|---|
| 27 | EE | Byungil Jeong,
Sungjoo Yoo,
Sunghyun Lee,
Kiyoung Choi:
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs.
ASP-DAC 2000: 169-174 |
| 26 | EE | Youngsoo Shin,
Kiyoung Choi:
Narrow bus encoding for low power systems.
ASP-DAC 2000: 217-220 |
| 25 | EE | Sungjoo Yoo,
Kyoungseok Rha,
Youngchul Cho,
Jinyong Jung,
Kiyoung Choi:
Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model.
CODES 2000: 77-81 |
| 24 | EE | Youngsoo Shin,
Daehong Kim,
Kiyoung Choi:
Schedulability-driven performance analysis of multiple mode embedded real-time systems.
DAC 2000: 495-500 |
| 23 | EE | Sungjoo Yoo,
Jong-eun Lee,
Jinyong Jung,
Kyungseok Rha,
Youngchul Cho,
Kiyoung Choi:
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor.
DATE 2000: 663-668 |
| 22 | | Youngsoo Shin,
Kiyoung Choi,
Takayasu Sakurai:
Power Optimization of Real-Time Embedded Systems on Variable Speed Processors.
ICCAD 2000: 365-368 |
| 21 | EE | Junghwan Choi,
Jinhwan Jeon,
Kiyoung Choi:
Power minimization of functional units partially guarded computation.
ISLPED 2000: 131-136 |
| 20 | EE | Jae-Hee Won,
Kiyoung Choi:
Low power self-timed Radix-2 division (poster session).
ISLPED 2000: 210-212 |
| 19 | EE | Sungjoo Yoo,
Kiyoung Choi,
Dong Sam Ha:
Performance improvement of geographically distributed cosimulation by hierarchically grouped messages.
IEEE Trans. VLSI Syst. 8(5): 492-502 (2000) |
| 1999 |
|---|
| 18 | EE | Sungjoo Yoo,
Kiyoung Choi:
Optimizing geographically distributed timed cosimulation by hierarchically grouped messages.
CODES 1999: 100-104 |
| 17 | EE | Youngsoo Shin,
Kiyoung Choi:
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems.
DAC 1999: 134-139 |
| 16 | EE | Sanghun Park,
Kiyoung Choi:
Performance-Driven Scheduling with Bit-Level Chaining.
DAC 1999: 286-291 |
| 15 | EE | Byungil Jeong,
Sungjoo Yoo,
Kiyoung Choi:
Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design.
FPGA 1999: 247 |
| 1998 |
|---|
| 14 | | Jinhwan Jeon,
Kiyoung Choi:
Loop Pipelining in Hardware-Software Partitioning.
ASP-DAC 1998: 361-366 |
| 13 | EE | Sungjoo Yoo,
Kiyoung Choi:
Optimistic distributed timed cosimulation based on thread simulation model.
CODES 1998: 71-75 |
| 12 | EE | Youngsoo Shin,
Kiyoung Choi:
Rate Assignment for Embedded Reactive Real-Time Systems.
EUROMICRO 1998: 10237- |
| 11 | EE | Youngsoo Shin,
Soo-Ik Chae,
Kiyoung Choi:
Partial bus-invert coding for power optimization of system level bus.
ISLPED 1998: 127-129 |
| 1997 |
|---|
| 10 | EE | Youngsoo Shin,
Kiyoung Choi:
Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign.
CODES 1997: 3-8 |
| 9 | EE | Daehong Kim,
Kiyoung Choi:
Power-conscious High Level Synthesis Using Loop Folding.
DAC 1997: 441-445 |
| 8 | EE | Dongwan Shin,
Kiyoung Choi:
Low power high level synthesis by increasing data correlation.
ISLPED 1997: 62-67 |
| 1996 |
|---|
| 7 | EE | Youngsoo Shin,
Kiyoung Choi:
Software synthesis through task decomposition by dependency analysis.
ICCAD 1996: 98-104 |
| 6 | EE | KiJong Lee,
Kiyoung Choi:
Self-timed divider based on RSD number system.
IEEE Trans. VLSI Syst. 4(2): 292-295 (1996) |
| 1995 |
|---|
| 5 | EE | Yongjoo Kim,
Kyuseok Kim,
Youngsoo Shin,
Taekyoon Ahn,
Wonyong Sung,
Kiyoung Choi,
Soonhoi Ha:
An integrated hardware-software cosimulation environment for heterogeneous systems prototyping.
ASP-DAC 1995 |
| 4 | | Yongjoo Kim,
Youngsoo Shin,
Kyuseok Kim,
Jae-Hee Won,
Kiyoung Choi:
Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification.
ISCAS 1995: 924-927 |
| 1994 |
|---|
| 3 | | Kiyoung Choi,
KiJong Lee,
Jun-Woo Kang:
A Self-Timed Divider Using RSD Number System.
ICCD 1994: 504-507 |
| 1988 |
|---|
| 2 | EE | Kiyoung Choi,
Sun Young Hwang,
Tom Blank:
Incremental-in-time Algorithm for Digital Simulation.
DAC 1988: 501-505 |
| 1 | EE | Sun Young Hwang,
Tom Blank,
Kiyoung Choi:
Fast functional simulation: an incremental approach.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(7): 765-774 (1988) |
