Tatsuo Ohtsuki

2008
36	EE	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: GECOM: Test data compression combined with all unknown response masking. ASP-DAC 2008: 577-582
35	EE	Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). ASP-DAC 2008: 697-702
34	EE	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Transactions 91-D(3): 776-780 (2008)
2007
33	EE	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS 2007: 149-152
2006
32	EE	Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ASP-DAC 2006: 594-599
31	EE	Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki: FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC 2006: 653-658
30	EE	Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki: Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Transactions 89-A(4): 996-1004 (2006)
29	EE	Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. IEICE Transactions 89-C(3): 243-249 (2006)
2005
28	EE	Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A processor core synthesis system in IP-based SoC design. ASP-DAC 2005: 286-291
27	EE	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura: Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium 2005: 386-389
26	EE	Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki: Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. ISCAS (4) 2005: 3499-3502
25	EE	Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. IEICE Transactions 88-A(4): 876-884 (2005)
24	EE	Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki: A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. IEICE Transactions 88-D(7): 1340-1349 (2005)
2004
23	EE	Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A cosynthesis algorithm for application specific processors with heterogeneous datapaths. ASP-DAC 2004: 250-255
22	EE	Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A thread partitioning algorithm in low power high-level synthesis. ASP-DAC 2004: 74-79
21	EE	Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki: Instruction set and functional unit synthesis for SIMD processor cores. ASP-DAC 2004: 743-750
20	EE	Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium 2004: 432-437
2002
19	EE	Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. APCCAS (1) 2002: 171-176
18	EE	Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: VLSI Architecture for a Flexible Motion Estimation with Parameters. VLSI Design 2002: 452-457
2001
17	EE	Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Area/delay estimation for digital signal processor cores. ASP-DAC 2001: 156-161
2000
16	EE	Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki: An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). ASP-DAC 2000: 309-312
1999
15	EE	Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki: A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. ASP-DAC 1999: 335-338
14	EE	Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki: A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. Journal of Circuits, Systems, and Computers 9(1-2): 09-112 (1999)
13	EE	Tingrong Zhao, Masao Yanagisawa, Tatsuo Ohtsuki: Fast Motion Estimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlations. Journal of Circuits, Systems, and Computers 9(1-2): 67-82 (1999)
1998
12		Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki: A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. ASP-DAC 1998: 265-274
11		Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki: An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. ASP-DAC 1998: 519-526
10	EE	Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 803-818 (1998)
1995
9	EE	Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki: Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. ASP-DAC 1995
1994
8	EE	Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki: A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. ICCAD 1994: 156-163
7		Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki: A Simultaneous Placement and Global Routing Algorithm for FPGAs. ISCAS 1994: 483-486
1992
6	EE	Toru Awashima, Wataru Yamamoto, Masao Sato, Tatsuo Ohtsuki: An optimal chip compaction method based on shortest path algorithm with automatic jog insertion. ICCAD 1992: 162-165
1990
5	EE	Masao Sato, Kazuto Kubota, Tatsuo Ohtsuki: A Hardware Implementation of Gridless Routing Based on Content Addressable Memory. DAC 1990: 646-649
1986
4	EE	Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki: A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 466-476 (1986)
1981
3		Tatsuo Ohtsuki, Hajimu Mori, Toshinobu Kashiwabara, Toshio Fujisawa: On Minimal Augmentation of a Graph to Obtain an Interval Graph. J. Comput. Syst. Sci. 22(1): 60-97 (1981)
1980
2		Tatsuo Ohtsuki: The two disjoint path problem and wire routing design. Graph Theory and Algorithms 1980: 207-216
1976
1		Tatsuo Ohtsuki: A Fast Algorithm for Finding an Optimal Ordering for Vertex Elimination on a Graph. SIAM J. Comput. 5(1): 133-145 (1976)

Coauthor Index

1	Toru Awashima	[6]
2	Jinku Choi	[18] [19]
3	Toshio Fujisawa	[3]
4	Kayoko Hagi	[11]
5	Takafumi Hisaki	[12]
6	Masayuki Ienaga	[16]
7	Toshinobu Kashiwabara	[3]
8	Yoshiharu Kataoka	[17]
9	Hideki Kawazu	[25] [26]
10	Shinji Kimura	[20] [27] [30] [31]
11	Shunitsu Kohara	[28] [32] [35]
12	Kazuto Kubota	[5]
13	Yusuke Matsunaga	[4]
14	Yuichiro Miyaoka	[17] [19] [21] [23] [24] [25] [26] [28] [32]
15	Hajimu Mori	[3]
16	Ryuta Nara	[35]
17	Takashi Sakurai	[15]
18	Masao Sato	[5] [6] [7] [8] [9]
19	Youhua Shi	[20] [27] [30] [31] [33] [34] [35] [36]
20	Kazunori Shimizu	[35]
21	Kei Suzuki	[4]
22	Masayoshi Tachibana	[4]
23	Koichi Tachikake	[21] [24]
24	Kazuyuki Tanimura	[35]
25	Nozomu Togawa	[7] [8] [9] [10] [11] [12] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36]
26	Naoki Tomono	[28] [32]
27	Jumpei Uchida	[22] [25] [26] [28] [29] [32]
28	Kaoru Ukai	[14]
29	Wataru Yamamoto	[6]
30	Masao Yanagisawa	[10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36]
31	Tingrong Zhao	[13]

Colors in the list of coauthors