Kazunori Shimizu

2008
13	EE	Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). ASP-DAC 2008: 697-702
12	EE	Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique. IEICE Transactions 91-A(4): 1054-1061 (2008)
11	EE	Qin Liu, Seiichiro Hiratsuka, Kazunori Shimizu, Shinsuke Ushiki, Satoshi Goto, Takeshi Ikenaga: A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems. IEICE Transactions 91-C(4): 449-456 (2008)
2007
10	EE	Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Power-efficient LDPC code decoder architecture. ISLPED 2007: 359-362
9	EE	Qi Wang, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto: Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms. IEICE Transactions 90-C(10): 1964-1971 (2007)
2006
8	EE	Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Memory-Efficient Accelerating Schedule for LDPC Decoder. APCCAS 2006: 1317-1320
7	EE	Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto: High-throughput decoder for low-density parity-check code. ASP-DAC 2006: 112-113
6	EE	Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: A parallel LSI architecture for LDPC decoder improving message-passing schedule. ISCAS 2006
5	EE	Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. IEICE Transactions 89-A(12): 3602-3612 (2006)
4	EE	Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule. IEICE Transactions 89-A(4): 969-978 (2006)
2005
3	EE	Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Reconfigurable adaptive FEC system with interleaving. ASP-DAC 2005: 1252-1255
2	EE	Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa: Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. ICCD 2005: 503-510
1	EE	Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving. IEICE Transactions 88-D(7): 1526-1537 (2005)

Coauthor Index

1	Satoshi Goto	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
2	Seiichiro Hiratsuka	[11]
3	Takeshi Ikenaga	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
4	Tatsuyuki Ishikawa	[2] [4] [5] [6] [7]
5	Shunitsu Kohara	[13]
6	Qin Liu	[11]
7	Ryuta Nara	[13]
8	Tatsuo Ohtsuki	[13]
9	Youhua Shi	[13]
10	Kazuyuki Tanimura	[13]
11	Nozomu Togawa	[1] [2] [3] [4] [5] [6] [8] [10] [12] [13]
12	Shinsuke Ushiki	[11]
13	Qi Wang	[9]
14	Masao Yanagisawa	[13]