2009 | ||
---|---|---|
54 | EE | Shingo Watanabe, Masanori Hashimoto, Toshinori Sato: A case for exploiting complex arithmetic circuits towards performance yield enhancement. ISQED 2009: 401-407 |
53 | EE | Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto: Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 541-553 (2009) |
2008 | ||
52 | EE | Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI 2008: 387-390 |
51 | EE | Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye: Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification. ASP-DAC 2008: 107-108 |
50 | EE | Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto: High performance current-mode differential logic. ASP-DAC 2008: 720-725 |
49 | EE | Takashi Enami, Masanori Hashimoto, Takashi Sato: Decoupling capacitance allocation for timing with statistical noise model and timing analysis. ICCAD 2008: 420-425 |
48 | EE | Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng: On-chip high performance signaling using passive compensation. ICCD 2008: 182-187 |
47 | EE | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED 2008: 3-8 |
46 | EE | Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto: Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise. ISPD 2008: 160-167 |
45 | EE | Shinya Abe, Masanori Hashimoto, Takao Onoye: Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. ISQED 2008: 520-525 |
44 | EE | Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera: Timing Analysis Considering Temporal Supply Voltage Fluctuation. IEICE Transactions 91-D(3): 655-660 (2008) |
2007 | ||
43 | EE | Kenichi Shinkai, Masanori Hashimoto, Takao Onoye: Future Prediction of Self-Heating in Short Intra-Block Wires. ISQED 2007: 660-665 |
42 | EE | Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera: Timing Analysis Considering Spatial Power/Ground Level Variation. IEICE Transactions 90-A(12): 2661-2668 (2007) |
41 | EE | Masanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa: Transistor Sizing of LCD Driver Circuit for Technology Migration. IEICE Transactions 90-A(12): 2712-2717 (2007) |
40 | EE | Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye: Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect. IEICE Transactions 90-A(4): 724-731 (2007) |
39 | EE | Hiroyuki Kobayashi, Nobuto Ono, Takashi Sato, Jiro Iwai, Hidenari Nakashima, Takaaki Okumura, Masanori Hashimoto: Proposal of Metrics for SSTA Accuracy Evaluation. IEICE Transactions 90-A(4): 808-814 (2007) |
38 | EE | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling. IEICE Transactions 90-C(6): 1267-1273 (2007) |
2006 | ||
37 | EE | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Interconnect RL extraction at a single representative frequency. ASP-DAC 2006: 515-520 |
36 | EE | Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye: A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. ICCAD 2006: 47-53 |
35 | EE | Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye: Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. ICCD 2006 |
34 | EE | Takashi Sato, Junji Ichimiya, Nobuto Ono, Masanori Hashimoto: On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature. IEICE Transactions 89-A(12): 3491-3499 (2006) |
33 | EE | Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa: A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays. IEICE Transactions 89-A(12): 3538-3545 (2006) |
32 | EE | Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto: Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Transactions 89-A(12): 3560-3568 (2006) |
31 | EE | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line. IEICE Transactions 89-A(12): 3585-3593 (2006) |
30 | EE | Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto: Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation. IEICE Transactions 89-A(12): 3666-3670 (2006) |
2005 | ||
29 | EE | Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa: Interconnect capacitance extraction for system LCD circuits. ACM Great Lakes Symposium on VLSI 2005: 160-163 |
28 | EE | Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto: On-chip thermal gradient analysis and temperature flattening for SoC design. ASP-DAC 2005: 1074-1077 |
27 | EE | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Return path selection for loop RL extraction. ASP-DAC 2005: 1078-1081 |
26 | EE | Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera: Timing analysis considering temporal supply voltage fluctuation. ASP-DAC 2005: 1098-1101 |
25 | EE | Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera: Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. ASP-DAC 2005: 723-728 |
24 | EE | Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera: Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. ASP-DAC 2005: 9-10 |
23 | EE | Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera: Effects of on-chip inductance on power distribution grid. ISPD 2005: 63-69 |
22 | EE | Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera: Statistical Analysis of Clock Skew Variation in H-Tree Structure. ISQED 2005: 402-407 |
21 | EE | Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera: Statistical Analysis of Clock Skew Variation in H-Tree Structure. IEICE Transactions 88-A(12): 3375-3381 (2005) |
20 | EE | Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto: On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design. IEICE Transactions 88-A(12): 3382-3389 (2005) |
19 | EE | Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera: Successive Pad Assignment for Minimizing Supply Voltage Drop. IEICE Transactions 88-A(12): 3429-3436 (2005) |
18 | EE | Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda: Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Transactions 88-A(12): 3453-3462 (2005) |
17 | EE | Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera: Effects of On-Chip Inductance on Power Distribution Grid. IEICE Transactions 88-A(12): 3564-3572 (2005) |
16 | EE | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling. IEICE Transactions 88-A(4): 885-891 (2005) |
15 | EE | Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera: A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL. IEICE Transactions 88-C(3): 437-444 (2005) |
2004 | ||
14 | EE | Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera: A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. ASP-DAC 2004: 545-546 |
13 | EE | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Representative frequency for interconnect R(f)L(f)C extraction. ASP-DAC 2004: 691-696 |
12 | EE | Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera: Timing analysis considering spatial power/ground level variation. ICCAD 2004: 814-820 |
11 | EE | Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera: Automatic Generation of Standard Cell Library in VDSM Technologies. ISQED 2004: 36-41 |
10 | EE | Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera: Equivalent waveform propagation for static timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 498-508 (2004) |
2003 | ||
9 | EE | Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera: Equivalent Waveform Propagation for Static Timing Analysis. ICCAD 2003: 169-175 |
8 | EE | Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera: Capturing crosstalk-induced waveform for accurate static timing analysis. ISPD 2003: 18-23 |
2002 | ||
7 | EE | Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera: Crosstalk noise optimization by post-layout transistor sizing. ISPD 2002: 126-130 |
6 | Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera: Experimental Study on Cell-Base High-Performance Datapath Design. IWLS 2002: 283-287 | |
2001 | ||
5 | EE | Masanori Hashimoto, Hidetoshi Onodera: Post-layout transistor sizing for power reduction in cell-based design. ASP-DAC 2001: 359-365 |
4 | Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera: Crosstalk Noise Estimation for Generic RC Trees. ICCD 2001: 110-117 | |
2000 | ||
3 | EE | Masanori Hashimoto, Hidetoshi Onodera: A performance optimization method by gate sizing using statistical static timing analysis. ISPD 2000: 111-116 |
1999 | ||
2 | EE | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru: A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC 1999: 446-451 |
1998 | ||
1 | EE | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru: A power optimization method considering glitch reduction by gate sizing. ISLPED 1998: 221-226 |