2006 | ||
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2 | EE | Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake, Yoshiki Tsukiboshi, Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami: Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems. ASP-DAC 2006: 533-540 |
1999 | ||
1 | EE | Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani: Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. ASP-DAC 1999: 125- |
1 | Hiroyuki Hara | [2] |
2 | Yoji Kajitani | [1] |
3 | Takeshi Kitahara | [2] |
4 | Fumihiro Minami | [2] |
5 | Shinichiro Shiratake | [2] |
6 | Atsushi Takahashi | [1] |
7 | Yoshiki Tsukiboshi | [2] |
8 | Tetsuaki Utsumi | [2] |