| 2009 |
| 28 | EE | Chun-Yu Chuang,
Wai-Kei Mak:
Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution.
ISQED 2009: 68-73 |
| 2008 |
| 27 | EE | Wei-Chung Chao,
Wai-Kei Mak:
Low-power gated and buffered clock network construction.
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 26 | EE | George A. Constantinides,
Wai-Kei Mak,
Theerayod Wiangtong:
Guest Editorial: Field Programmable Technology.
Signal Processing Systems 51(1): 1-2 (2008) |
| 2007 |
| 25 | EE | Wai-Kei Mak,
Jr-Wei Chen:
Voltage Island Generation under Performance Requirement for SoC Designs.
ASP-DAC 2007: 798-803 |
| 2006 |
| 24 | EE | Chien-Chang Chen,
Wai-Kei Mak:
A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers.
ASP-DAC 2006: 777-782 |
| 2005 |
| 23 | EE | Wai-Kei Mak:
Modern FPGA constrained placement.
ASP-DAC 2005: 779-784 |
| 2004 |
| 22 | EE | Hao Li,
Wai-Kei Mak,
Srinivas Katkoori:
Force-Directed Performance-Driven Placement Algorithm for FPGAs.
ISVLSI 2004: 193-198 |
| 21 | EE | Hao Li,
Srinivas Katkoori,
Wai-Kei Mak:
Power minimization algorithms for LUT-based FPGA technology mapping.
ACM Trans. Design Autom. Electr. Syst. 9(1): 33-51 (2004) |
| 20 | EE | Wai-Kei Mak:
I/O placement for FPGAs with multiple I/O standards.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 315-321 (2004) |
| 2003 |
| 19 | EE | Eric S. H. Wong,
Evangeline F. Y. Young,
Wai-Kei Mak:
Clustering based acyclic multi-way partitioning.
ACM Great Lakes Symposium on VLSI 2003: 203-206 |
| 18 | EE | Wai-Kei Mak:
I/O placement for FPGAs with multiple I/O standards.
FPGA 2003: 51-57 |
| 17 | EE | Wai-Kei Mak,
Evangeline F. Y. Young:
Temporal logic replication for dynamically reconfigurable FPGA partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 952-959 (2003) |
| 2002 |
| 16 | EE | Wai-Kei Mak,
Evangeline F. Y. Young:
Temporal logic replication for dynamically reconfigurable FPGA partitioning.
ISPD 2002: 190-195 |
| 15 | EE | Wai-Kei Mak:
Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 491-497 (2002) |
| 2001 |
| 14 | EE | Hung-Ming Chen,
D. F. Wong,
Wai-Kei Mak,
Hannah Honghua Yang:
Faster and more accurate wiring evaluation in interconnect-centric floorplanning.
ACM Great Lakes Symposium on VLSI 2001: 62-67 |
| 13 | EE | Wai-Kei Mak:
Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead.
ISPD 2001: 100-105 |
| 2000 |
| 12 | EE | Wai-Kei Mak,
D. F. Wong:
A fast hypergraph min-cut algorithm for circuit partitioning.
Integration 30(1): 1-11 (2000) |
| 1999 |
| 11 | EE | Wai-Kei Mak,
D. F. Wong:
A fast hypergraph minimum cut algorithm.
ISCAS (6) 1999: 170-173 |
| 10 | EE | Wai-Kei Mak,
David P. Morton,
R. Kevin Wood:
Monte Carlo bounding techniques for determining solution quality in stochastic programs.
Oper. Res. Lett. 24(1-2): 47-56 (1999) |
| 1998 |
| 9 | EE | Wai-Kei Mak,
D. F. Wong:
Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract).
FPGA 1998: 260 |
| 1997 |
| 8 | | Wai-Kei Mak,
D. F. Wong:
Channel Segmentation Design for Symmentrical FPGAs.
ICCD 1997: 496-501 |
| 7 | EE | Wai-Kei Mak,
D. F. Wong:
Board-level multiterminal net routing for FPGA-based logic emulation.
ACM Trans. Design Autom. Electr. Syst. 2(2): 151-167 (1997) |
| 6 | EE | Wai-Kei Mak,
Martin D. F. Wong:
Minimum replication min-cut partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1221-1227 (1997) |
| 5 | EE | Wai-Kei Mak,
Martin D. F. Wong:
On optimal board-level routing for FPGA-based logic emulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 282-289 (1997) |
| 1996 |
| 4 | EE | Wai-Kei Mak,
D. F. Wong:
Minimum replication min-cut partitioning.
ICCAD 1996: 205-210 |
| 1995 |
| 3 | EE | Wai-Kei Mak,
D. F. Wong:
On Optimal Board-Level Routing for FPGA-Based Logic Emulation.
DAC 1995: 552-556 |
| 2 | EE | Wai-Kei Mak,
D. F. Wong:
Board-level multi-terminal net routing for FPGA-based logic emulation.
ICCAD 1995: 339-344 |
| 1990 |
| 1 | | Richard G. Guy,
John S. Heidemann,
Wai-Kei Mak,
Thomas W. Page Jr.,
Gerald J. Popek,
Dieter Rothmeier:
Implementation of the Ficus Replicated File System.
USENIX Summer 1990: 63-72 |