| 2008 |
|---|
| 75 | EE | Ngok-Man Sze,
Wing-Hung Ki,
Chi-Ying Tsui:
Threshold Voltage Start-up Boost Converter for Sub-mA Applications.
DELTA 2008: 338-341 |
| 74 | EE | Ngok-Man Sze,
Feng Su,
Yat-Hei Lam,
Wing-Hung Ki,
Chi-Ying Tsui:
Integrated single-inductor dual-input dual-output boost converter for energy harvesting applications.
ISCAS 2008: 2218-2221 |
| 73 | EE | Jun Yi,
Feng Su,
Yat-Hei Lam,
Wing-Hung Ki,
Chi-Ying Tsui:
An energy-adaptive MPPT power management unit for micro-power vibration energy harvesting.
ISCAS 2008: 2570-2573 |
| 72 | EE | Jie Jin,
Chi-Ying Tsui:
A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes.
ISLPED 2008: 253-258 |
| 71 | EE | Ricky Yiu-kee Choi,
Chi-Ying Tsui:
A Low Energy Two-Step Successive Approximation Algorithm for ADC Design.
ISQED 2008: 317-320 |
| 70 | EE | Chi-Ying Tsui,
Robert Yi-Ching Au,
Ricky Yiu-kee Choi:
Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping.
Integration 41(1): 76-86 (2008) |
| 2007 |
|---|
| 69 | EE | Lap-Fai Leung,
Chi-Ying Tsui:
Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands.
DAC 2007: 128-131 |
| 68 | EE | Lu Chao,
Chi-Ying Tsui,
Wing-Hung Ki:
A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous Applications.
ISCAS 2007: 1349-1352 |
| 67 | EE | Hui Shao,
Chi-Ying Tsui,
Wing-Hung Ki:
An Inductor-less Micro Solar Power Management System Design for Energy Harvesting Applications.
ISCAS 2007: 1353-1356 |
| 66 | EE | Hui Shao,
Chi-Ying Tsui,
Wing-Hung Ki:
A micro power management system and maximum output power control for solar energy harvesting applications.
ISLPED 2007: 298-303 |
| 65 | EE | Lu Chao,
Chi-Ying Tsui,
Wing-Hung Ki:
Vibration energy scavenging and management for ultra low power applications.
ISLPED 2007: 316-321 |
| 64 | EE | Wei-Feng He,
Meng-Lian Zhao,
Chi-Ying Tsui,
Zhi-Gang Mao:
A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation.
VLSI Design 2007: 830-835 |
| 63 | EE | Lap-Fai Leung,
Chi-Ying Tsui,
Xiaobo Sharon Hu:
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling
CoRR abs/0710.4758: (2007) |
| 62 | EE | Jie Jin,
Chi-Ying Tsui:
Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition.
IEEE Trans. VLSI Syst. 15(10): 1172-1176 (2007) |
| 2006 |
|---|
| 61 | EE | Yat-Hei Lam,
Suet-Chui Koon,
Wing-Hung Ki,
Chi-Ying Tsui:
Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors.
ASP-DAC 2006: 102-103 |
| 60 | EE | Yat-Hei Lam,
Wing-Hung Ki,
Chi-Ying Tsui:
Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback.
ASP-DAC 2006: 104-105 |
| 59 | EE | Chi-Ying Tsui,
Hui Shao,
Wing-Hung Ki,
Feng Su:
Ultra-low voltage power management circuit and computation methodology for energy harvesting applications.
ASP-DAC 2006: 96-97 |
| 58 | EE | Lap-Fai Leung,
Chi-Ying Tsui:
Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems.
DAC 2006: 833-838 |
| 57 | EE | Hui Shao,
Chi-Ying Tsui,
Wing-Hung Ki:
A charge based computation system and control strategy for energy harvesting applications.
ISCAS 2006 |
| 56 | EE | Feng Liu,
Chi-Ying Tsui:
Energy-aware optimal workload allocation among the battery-powered devices to maximize the co-operation life time.
ISCAS 2006 |
| 55 | EE | Feng Su,
Wing-Hung Ki,
Chi-Ying Tsui:
High efficiency cross-coupled doubler with no reversion loss.
ISCAS 2006 |
| 54 | EE | Hing-mo Lam,
Chi-Ying Tsui:
High performance single clock cycle CMOS comparator.
ISCAS 2006 |
| 53 | EE | Jie Jin,
Chi-Ying Tsui:
A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications.
ISLPED 2006: 406-411 |
| 52 | EE | Jin Jie,
Chi-Ying Tsui:
Low Complexity SST Viterbi Decoder.
VTC Fall 2006: 1-2 |
| 2005 |
|---|
| 51 | EE | Lap-Fai Leung,
Chi-Ying Tsui,
Xiaobo Sharon Hu:
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling.
DATE 2005: 634-639 |
| 50 | EE | Feng Liu,
Chi-Ying Tsui:
A Data Discarding Framework for Reducing the Energy Consumption of Viterbi Decoder in Decoding Broadcasted Wireless Multi-Resolution JPEG2000 Images.
ESTImedia 2005: 21-26 |
| 49 | EE | Wing-Hung Ki,
Feng Su,
Chi-Ying Tsui:
Charge redistribution loss consideration in optimal charge pump design.
ISCAS (2) 2005: 1895-1898 |
| 48 | EE | Feng Su,
Wing-Hung Ki,
Chi-Ying Tsui:
Gate control strategies for high efficiency charge pumps.
ISCAS (2) 2005: 1907-1910 |
| 47 | EE | Jin Jie,
Chi-Ying Tsui,
Wai Ho Mow:
A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems.
ISCAS (4) 2005: 3359-3362 |
| 2004 |
|---|
| 46 | EE | Yan Wang,
Chi-Ying Tsui,
Roger S. Cheng,
Wai Ho Mow:
Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacity.
ASP-DAC 2004: 125-130 |
| 45 | EE | Dongsheng Ma,
Wing-Hung Ki,
Chi-Ying Tsui:
Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process.
ASP-DAC 2004: 539-540 |
| 44 | EE | Martin Yeung-Kei Chui,
Wing-Hung Ki,
Chi-Ying Tsui:
A dual--band switching digital controller for a buck converter.
ASP-DAC 2004: 561-562 |
| 43 | EE | Lap-Fai Leung,
Chi-Ying Tsui,
Wing-Hung Ki:
Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignment.
ASP-DAC 2004: 647-652 |
| 42 | EE | Lap-Fai Leung,
Chi-Ying Tsui,
Wing-Hung Ki:
Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical data.
ASP-DAC 2004: 663-665 |
| 41 | EE | Siu-Kei Wong,
Chi-Ying Tsui:
Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus.
DATE 2004: 130-135 |
| 40 | | Feng Liu,
Chi-Ying Tsui:
Adaptive spectrum-based variable bit truncation of discrete cosine transform (DCT) for energy-efficient wireless multimedia communication.
ESTImedia 2004: 81-86 |
| 39 | | Siu-Kei Wong,
Chi-Ying Tsui:
Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus.
ISCAS (2) 2004: 321-324 |
| 38 | | Robert Yi-Ching Au,
Chi-Ying Tsui:
Least leakage vector assisted technology mapping for total power optimization.
ISCAS (5) 2004: 145-148 |
| 37 | EE | Lap-Fai Leung,
Chi-Ying Tsui,
Xiaobo Sharon Hu:
Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling.
PATMOS 2004: 553-563 |
| 2003 |
|---|
| 36 | EE | Chun Kit Hung,
Mounir Hamdi,
Chi-Ying Tsui:
Design and implementation of high-speed arbiter for large scale VOQ crossbar switches.
ISCAS (2) 2003: 308-311 |
| 35 | EE | Yat-Hei Lam,
Wing-Hung Ki,
Chi-Ying Tsui,
Philip K. T. Mok:
Single-inductor dual-input dual-output switching converter for integrated battery charging and power regulation.
ISCAS (3) 2003: 447-450 |
| 34 | EE | Lap-Fai Leung,
Chi-Ying Tsui,
Wing-Hung Ki:
Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming.
ISCAS (5) 2003: 309-312 |
| 33 | EE | Hing-mo Lam,
Chi-Ying Tsui:
High performance and low power completion detection circuit.
ISCAS (5) 2003: 405-408 |
| 2002 |
|---|
| 32 | EE | Jing Liu,
Chun Kit Hung,
Mounir Hamdi,
Chi-Ying Tsui:
Stable Round-Robin Scheduling Algorithms for High-Performance Input Queued Switches.
Hot Interconnects 2002: 43-51 |
| 31 | EE | Kwan-wai Wong,
Chi-Ying Tsui,
R. S.-K. Cheng,
Wai Ho Mow:
A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels.
ISCAS (3) 2002: 273-276 |
| 30 | EE | Yan Wang,
Hing Mo Lam,
Chi-Ying Tsui,
Roger S. Cheng,
Wai Ho Mow:
Low complexity OFDM receiver using Log-FFT for coded OFDM system.
ISCAS (3) 2002: 445-448 |
| 2001 |
|---|
| 29 | EE | Dongsheng Ma,
Wing-Hung Ki,
Chi-Ying Tsui,
Philip K. T. Mok:
A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling.
ASP-DAC 2001: 19-20 |
| 28 | EE | Dongsheng Ma,
Wing-Hung Ki,
Philip K. T. Mok,
Chi-Ying Tsui:
Single-inductor multiple-output switching converters with bipolar outputs.
ISCAS (3) 2001: 301-304 |
| 27 | EE | Oliver Yuk-Hang Leung,
Chi-Ying Tsui,
R. S.-K. Cheng:
Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage.
IEEE Trans. VLSI Syst. 9(1): 34-41 (2001) |
| 2000 |
|---|
| 26 | EE | Oliver Yuk-Hang Leung,
Chi-Ying Tsui,
Roger S. Cheng:
VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGA.
ASP-DAC 2000: 3-4 |
| 25 | EE | Chi-Ying Tsui,
Louis Chung-Yin Kwan,
Chin-Tau Lea:
VLSI implementation of a switch fabric for mixed ATM and IP traffic.
ASP-DAC 2000: 5-6 |
| 24 | | Zhong-Li He,
Chi-Ying Tsui,
Kai-Keung Chan,
Ming L. Liou:
Low-power VLSI design for motion estimation using adaptive pixel truncation.
IEEE Trans. Circuits Syst. Video Techn. 10(5): 669-678 (2000) |
| 1999 |
|---|
| 23 | EE | Massoud Pedram,
Chi-Ying Tsui,
Qing Wu:
An Integrated Battery-Hardware Model for Portable Electronics.
ASP-DAC 1999: 109- |
| 22 | EE | Chun-hong Chen,
Chi-Ying Tsui:
Timing Optimization of Logic Network Using Gate Duplication.
ASP-DAC 1999: 233-236 |
| 21 | EE | Chi-Ying Tsui,
R. S.-K. Cheng,
C. Ling:
Low power ACS unit design for the Viterbi decoder [CDMA wireless systems].
ISCAS (1) 1999: 137-140 |
| 20 | EE | Wai-Kwong Lee,
Chi-Ying Tsui:
Finite state machine partitioning for low power.
ISCAS (1) 1999: 306-309 |
| 19 | EE | Chi Wai Yung,
Hung Fai Fu,
Chi-Ying Tsui,
Roger S. Cheng,
D. George:
Unequal error protection for wireless transmission of MPEG audio.
ISCAS (6) 1999: 342-345 |
| 18 | EE | Oliver Yuk-Hang Leung,
Chung-Wai Yue,
Chi-Ying Tsui,
Roger S. Cheng:
Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage.
ISLPED 1999: 36-41 |
| 1998 |
|---|
| 17 | EE | Chun-hong Chen,
Chi-Ying Tsui:
Towards the capability of providing power-area-delay trade-off at the register transfer level.
ISLPED 1998: 24-29 |
| 16 | EE | Chih-Shun Ding,
Chi-Ying Tsui,
Massoud Pedram:
Gate-level power estimation using tagged probabilistic simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1099-1107 (1998) |
| 15 | EE | Chi-Ying Tsui,
Massoud Pedram,
Alvin M. Despain:
Low-power state assignment targeting two- and multilevel logic implementations.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1281-1291 (1998) |
| 14 | EE | Chi-Ying Tsui,
Massoud Pedram:
Accurate and efficient power simulation strategy by compacting the input vector set.
Integration 25(1): 37-52 (1998) |
| 1997 |
|---|
| 13 | EE | Chi-Ying Tsui,
Kai-Keung Chan,
Qing Wu,
Chih-Shun Ding,
Massoud Pedram:
A Power Estimation Framework for Designing Low Power Portable Video Applications.
DAC 1997: 421-424 |
| 12 | EE | Zhong-Li He,
Kai-Keung Chan,
Chi-Ying Tsui,
Ming L. Liou:
Low power motion estimation design using adaptive pixel truncation.
ISLPED 1997: 167-172 |
| 1996 |
|---|
| 11 | EE | Chi-Ying Tsui,
Radu Marculescu,
Diana Marculescu,
Massoud Pedram:
Improving the Efficiency of Power Simulators by Input Vector Compaction.
DAC 1996: 165-168 |
| 10 | EE | Chi-Ying Tsui,
José C. Monteiro,
Massoud Pedram,
Srinivas Devadas,
Alvin M. Despain,
Bill Lin:
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].
IEEE Trans. VLSI Syst. 4(4): 495 (1996) |
| 1995 |
|---|
| 9 | EE | Chi-Ying Tsui,
José C. Monteiro,
Massoud Pedram,
Srinivas Devadas,
Alvin M. Despain,
Bill Lin:
Power estimation methods for sequential logic circuits.
IEEE Trans. VLSI Syst. 3(3): 404-416 (1995) |
| 1994 |
|---|
| 8 | | Ching-Long Su,
Chi-Ying Tsui,
Alvin M. Despain:
Lower Power Architecture Design and Compilation Techniques for High-Performance Processors.
COMPCON 1994: 489-498 |
| 7 | EE | Chi-Ying Tsui,
Massoud Pedram,
Alvin M. Despain:
Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs.
DAC 1994: 18-23 |
| 6 | EE | Chi-Ying Tsui,
Massoud Pedram,
Chih-Ang Chen,
Alvin M. Despain:
Low power state assignment targeting two-and multi-level logic implementations.
ICCAD 1994: 82-87 |
| 5 | EE | Ching-Long Su,
Chi-Ying Tsui,
Alvin M. Despain:
Saving Power in the Control Path of Embedded Processors.
IEEE Design & Test of Computers 11(4): 24-30 (1994) |
| 4 | EE | Chi-Ying Tsui,
Massoud Pedram,
Alvin M. Despain:
Power efficient technology decomposition and mapping under an extended power consumption model.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1110-1122 (1994) |
| 1993 |
|---|
| 3 | EE | Chi-Ying Tsui,
Massoud Pedram,
Alvin M. Despain:
Technology Decomposition and Mapping Targeting Low Power Dissipation.
DAC 1993: 68-73 |
| 2 | EE | Chi-Ying Tsui,
Massoud Pedram,
Alvin M. Despain:
Efficient estimation of dynamic power consumption under a real delay model.
ICCAD 1993: 224-228 |
| 1992 |
|---|
| 1 | EE | Iksoo Pyo,
Ching-Long Su,
Ing-Jer Huang,
Kuo-Rueih Pan,
Yong-Seon Koh,
Chi-Ying Tsui,
Hsu-Tsun Chen,
Gino Cheng,
Shihming Liu,
Shiqun Wu,
Alvin M. Despain:
Application-Driven Design Automation for Microprocessor Design.
DAC 1992: 512-517 |
