2007 |
7 | EE | A. Amirabadi,
Ali Afzali-Kusha,
Y. Mortazavi,
Mehrdad Nourani:
Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper.
IEEE Trans. VLSI Syst. 15(2): 125-134 (2007) |
2006 |
6 | EE | S. H. Rasouli,
A. Amirabadi,
A. Seyedi,
Ali Afzali-Kusha:
Double edge triggered Feedback Flip-Flop in sub 100NM technology.
ASP-DAC 2006: 297-302 |
5 | EE | A. Amirabadi,
A. Chehelcheraghi,
S. H. Rasouli,
A. Seyedi,
Ali Afzali-Kusha:
Low power and high performance clock delayed domino logic using saturated keeper.
ISCAS 2006 |
4 | EE | A. S. Seyedi,
S. H. Rasouli,
A. Amirabadi,
Ali Afzali-Kusha:
Low power low leakage clock gated static pulsed flip-flop.
ISCAS 2006 |
3 | EE | A. S. Seyedi,
S. H. Rasouli,
A. Amirabadi,
Ali Afzali-Kusha:
Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology.
ISVLSI 2006: 373-377 |
2005 |
2 | EE | A. Amirabadi,
Y. Mortazavi,
Nariman Moezzi Madani,
Ali Afzali-Kusha,
Mehrdad Nourani:
Domino logic with an efficient variable threshold voltage keeper.
ISCAS (2) 2005: 1674-1677 |
2004 |
1 | EE | A. Amirabadi,
Javid Jaffari,
Ali Afzali-Kusha,
Mehrdad Nourani,
Ali Khaki-Firooz:
Leakage current reduction by new technique in standby mode.
ACM Great Lakes Symposium on VLSI 2004: 158-161 |