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A. Amirabadi

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2007
7EEA. Amirabadi, Ali Afzali-Kusha, Y. Mortazavi, Mehrdad Nourani: Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper. IEEE Trans. VLSI Syst. 15(2): 125-134 (2007)
2006
6EES. H. Rasouli, A. Amirabadi, A. Seyedi, Ali Afzali-Kusha: Double edge triggered Feedback Flip-Flop in sub 100NM technology. ASP-DAC 2006: 297-302
5EEA. Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, Ali Afzali-Kusha: Low power and high performance clock delayed domino logic using saturated keeper. ISCAS 2006
4EEA. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha: Low power low leakage clock gated static pulsed flip-flop. ISCAS 2006
3EEA. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha: Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology. ISVLSI 2006: 373-377
2005
2EEA. Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani: Domino logic with an efficient variable threshold voltage keeper. ISCAS (2) 2005: 1674-1677
2004
1EEA. Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz: Leakage current reduction by new technique in standby mode. ACM Great Lakes Symposium on VLSI 2004: 158-161

Coauthor Index

1Ali Afzali-Kusha [1] [2] [3] [4] [5] [6] [7]
2A. Chehelcheraghi [5]
3Javid Jaffari [1]
4Ali Khaki-Firooz [1]
5Nariman Moezzi Madani [2]
6Y. Mortazavi [2] [7]
7Mehrdad Nourani [1] [2] [7]
8S. H. Rasouli [3] [4] [5] [6]
9A. Seyedi [5] [6]
10A. S. Seyedi [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)