2009 |
19 | EE | Jeff L. Cobb,
Kanupriya Gulati,
Sunil P. Khatri:
Robust window-based multi-node technology-independent logic minimization.
ACM Great Lakes Symposium on VLSI 2009: 357-362 |
18 | EE | Kalyana C. Bollapalli,
Rajesh Garg,
Kanupriya Gulati,
Sunil P. Khatri:
Low power and high performance sram design using bank-based selective forward body bias.
ACM Great Lakes Symposium on VLSI 2009: 441-444 |
17 | EE | Kanupriya Gulati,
Sunil P. Khatri,
Peng Li:
Closed-loop modeling of power and temperature profiles of FPGAs.
FPGA 2009: 287 |
16 | EE | Kanupriya Gulati,
Suganth Paul,
Sunil P. Khatri,
Srinivas Patil,
Abhijit Jas:
FPGA-based hardware acceleration for Boolean satisfiability.
ACM Trans. Design Autom. Electr. Syst. 14(2): (2009) |
2008 |
15 | EE | Kanupriya Gulati,
Sunil P. Khatri:
Improving FPGA routability using network coding.
ACM Great Lakes Symposium on VLSI 2008: 147-150 |
14 | EE | Kanupriya Gulati,
Sunil P. Khatri:
Towards acceleration of fault simulation using graphics processing units.
DAC 2008: 822-827 |
13 | EE | Nikhil Saluja,
Kanupriya Gulati,
Sunil P. Khatri:
SAT-based ATPG using multilevel compatible don't-cares.
ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
12 | EE | Kanupriya Gulati,
Nikhil Jayakumar,
Sunil P. Khatri,
D. M. H. Walker:
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations.
Integration 41(3): 399-412 (2008) |
2007 |
11 | EE | Eugene Goldberg,
Kanupriya Gulati:
On Complexity of Internal and External Equivalence Checking.
DSD 2007: 197-206 |
10 | EE | Eugene Goldberg,
Kanupriya Gulati,
Sunil P. Khatri:
Toggle Equivalence Preserving (TEP) Logic Optimization.
DSD 2007: 271-279 |
9 | EE | Kanupriya Gulati,
Nikhil Jayakumar,
Sunil P. Khatri:
A Structured ASIC Design Approach Using Pass Transistor Logic.
ISCAS 2007: 1787-1790 |
2006 |
8 | EE | Rajesh Garg,
Mario Sanchez,
Kanupriya Gulati,
Nikhil Jayakumar,
Anshul Gupta,
Sunil P. Khatri:
A design flow to optimize circuit delay by using standard cells and PLAs.
ACM Great Lakes Symposium on VLSI 2006: 217-222 |
7 | EE | Brock J. LaMeres,
Kanupriya Gulati,
Sunil P. Khatri:
Controlling inductive cross-talk and power in off-chip buses using CODECs.
ASP-DAC 2006: 850-855 |
6 | EE | Nikhil Jayakumar,
Sunil P. Khatri,
Kanupriya Gulati,
Alexander Sprintson:
Network coding for routability improvement in VLSI.
ICCAD 2006: 820-823 |
5 | EE | Mandar Waghmode,
Kanupriya Gulati,
Sunil P. Khatri,
Weiping Shi:
An Efficient, Scalable Hardware Engine for Boolean SATisfiability.
ICCD 2006 |
4 | EE | Kanupriya Gulati,
Nikhil Jayakumar,
Sunil P. Khatri:
A probabilistic method to determine the minimum leakage vector for combinational designs.
ISCAS 2006 |
3 | EE | Kanupriya Gulati,
M. Lovell,
Sunil P. Khatri:
Efficient don't care computation for hierarchical designs.
ISCAS 2006 |
2 | EE | Chunjie Duan,
Kanupriya Gulati,
Sunil P. Khatri:
Memory-based crosstalk canceling CODECs for on-chip buses.
ISCAS 2006 |
2005 |
1 | EE | Kanupriya Gulati,
Nikhil Jayakumar,
Sunil P. Khatri:
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs.
ISLPED 2005: 111-114 |