2009 |
20 | EE | Mehrtash Manoochehri,
Alireza Ejlali,
Seyed Ghassem Miremadi:
Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-off.
ISQED 2009: 839-844 |
2008 |
19 | EE | Hamed Tabkhi,
Seyed Ghassem Miremadi,
Alireza Ejlali:
An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors.
DFT 2008: 445-453 |
18 | EE | Mehrdad Khatir,
Amir Moradi,
Alireza Ejlali,
Mohammad T. Manzuri Shalmani,
Mahmoud Salmasizadeh:
A secure and low-energy logic style using charge recovery approach.
ISLPED 2008: 259-264 |
17 | EE | Alireza Ejlali,
Bashir M. Al-Hashimi:
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks.
NOCS 2008: 67-76 |
2007 |
16 | EE | Alireza Ejlali,
Bashir M. Al-Hashimi,
Paul M. Rosinger,
Seyed Ghassem Miremadi:
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks.
DATE 2007: 1647-1652 |
15 | EE | Mahdi Fazeli,
Ahmad Patooghy,
Seyed Ghassem Miremadi,
Alireza Ejlali:
Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies.
DSN 2007: 276-285 |
2006 |
14 | EE | Yuan Cai,
Marcus T. Schmitz,
Alireza Ejlali,
Bashir M. Al-Hashimi,
Sudhakar M. Reddy:
Cache size selection for performance, energy and reliability of time-constrained systems.
ASP-DAC 2006: 923-928 |
13 | EE | Alireza Ejlali,
Bashir M. Al-Hashimi,
Marcus T. Schmitz,
Paul M. Rosinger,
Seyed Ghassem Miremadi:
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.
IEEE Trans. VLSI Syst. 14(4): 323-335 (2006) |
2005 |
12 | EE | Alireza Ejlali,
Marcus T. Schmitz,
Bashir M. Al-Hashimi,
Seyed Ghassem Miremadi,
Paul M. Rosinger:
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy.
ISLPED 2005: 281-286 |
11 | | Somayeh Timarchi,
Seyed Ghassem Miremadi,
Ali Reza Ejlali:
Evaluation of Some Exponential Random Number Generators Implemented by FPGA.
Parallel and Distributed Computing and Networks 2005: 578-583 |
2004 |
10 | | Hamid R. Zarandi,
Seyed Ghassem Miremadi,
Shaahin Hessabi,
Ali Reza Ejlali:
A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models.
ESA/VLSI 2004: 582-588 |
9 | EE | Ghazanfar Asadi,
Seyed Ghassem Miremadi,
Hamid R. Zarandi,
Ali Reza Ejlali:
Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs.
PRDC 2004: 327-332 |
8 | EE | Alireza Ejlali,
Seyed Ghassem Miremadi:
FPGA-based Monte Carlo simulation for fault tree analysis.
Microelectronics Reliability 44(6): 1017-1028 (2004) |
7 | EE | Alireza Ejlali,
Seyed Ghassem Miremadi:
FPGA-based fault injection into switch-level models.
Microprocessors and Microsystems 28(5-6): 317-327 (2004) |
2003 |
6 | EE | Ali Reza Ejlali,
Seyed Ghassem Miremadi:
Switch-level emulation.
DAC 2003: 644-649 |
5 | EE | Hamid R. Zarandi,
Seyed Ghassem Miremadi,
Ali Reza Ejlali:
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models.
DFT 2003: 485-492 |
4 | EE | Ali Reza Ejlali,
Seyed Ghassem Miremadi,
Hamid R. Zarandi,
Ghazanfar Asadi,
Siavash Bayat Sarmadi:
A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation.
DSN 2003: 479- |
3 | EE | Seyed Ghassem Miremadi,
Ali Reza Ejlali:
Switch Level Fault Emulation.
FPL 2003: 849-858 |
2 | EE | Hamid R. Zarandi,
Seyed Ghassem Miremadi,
Ali Reza Ejlali:
Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems.
ISPDC 2003: 281- |
2002 |
1 | EE | Siavash Bayat Sarmadi,
Seyed Ghassem Miremadi,
Ghazanfar Asadi,
Ali Reza Ejlali:
Fast Prototyping with Co-operation of Simulation and Emulation.
FPL 2002: 15-25 |