Yoshinobu Higami

2009
33	EE	Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume: A Novel Approach for Improving the Quality of Open Fault Diagnosis. VLSI Design 2009: 85-90
32	EE	Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu: Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. VLSI Design 2009: 91-96
2008
31	EE	Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki: Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information. IEICE Transactions 91-D(3): 675-682 (2008)
30	EE	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. IEICE Transactions 91-D(3): 690-699 (2008)
29	EE	Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Post-BIST Fault Diagnosis for Multiple Faults. IEICE Transactions 91-D(3): 771-775 (2008)
2007
28	EE	Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu: Timing-Aware Diagnosis for Small Delay Defects. DFT 2007: 223-234
27	EE	Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume: Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. DFT 2007: 243-251
26	EE	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu: Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. VLSI Design 2007: 781-786
2006
25	EE	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. ASP-DAC 2006: 659-664
24	EE	Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT 2006: 401-109
23	EE	Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu: On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Transactions 89-D(11): 2748-2755 (2006)
2005
22	EE	T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu: On the fault diagnosis in the presence of unknown fault models using pass/fail information. ISCAS (3) 2005: 2987-2990
21	EE	Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu: Test cost reduction for logic circuits: Reduction of test data volume and test application time. Systems and Computers in Japan 36(6): 69-83 (2005)
2004
20	EE	Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu: Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. Asian Test Symposium 2004: 216-221
19	EE	Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu: Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. Asian Test Symposium 2004: 222-227
18	EE	Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu: Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. Asian Test Symposium 2004: 46-49
2003
17	EE	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz: A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ICCD 2003: 397-
2002
16	EE	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu: A Method to Reduce Power Dissipation during Test for Sequential Circuits. Asian Test Symposium 2002: 326-331
15	EE	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu: Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. DELTA 2002: 431-433
2001
14	EE	Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu: Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. Asian Test Symposium 2001: 63-
13	EE	Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu: Test Generation for Double Stuck-at Faults. Asian Test Symposium 2001: 71-75
2000
12	EE	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Fault models and test generation for IDDQ testing: embedded tutorial. ASP-DAC 2000: 509-514
11	EE	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita: Test sequence compaction for sequential circuits with reset states. Asian Test Symposium 2000: 165-170
10	EE	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electronic Testing 16(5): 443-451 (2000)
9	EE	Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita: Static test compaction for IDDQ testing of bridging faults in sequential circuits. Systems and Computers in Japan 31(11): 41-50 (2000)
1999
8	EE	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 141-146
7		Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita: Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. VLSI Design 1999: 72-77
1998
6	EE	Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita: Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. Asian Test Symposium 1998: 312-317
1997
5	EE	Yoshinobu Higami, Kozo Kinoshita: Design of partially parallel scan chain. ED&TC 1997: 626
1996
4	EE	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium 1996: 94-99
1995
3	EE	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Test sequence compaction by reduced scan shift and retiming. Asian Test Symposium 1995: 169-175
2	EE	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Partial scan design and test sequence generation based on reduced scan shift method. J. Electronic Testing 7(1-2): 115-124 (1995)
1994
1		Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Reduced Scan Shift: A New Testing Method for Sequential Circuit. ITC 1994: 624-630

Coauthor Index

1	Takashi Aikyo	[24] [27] [28] [29] [31] [32] [33]
2	Masaki Hashizume	[27] [32] [33]
3	Hideyuki Ichihara	[21]
4	Shuhei Kadoyama	[24] [29]
5	Seiji Kajihara	[1] [2] [3] [4] [17] [18] [21] [23]
6	Toru Kikkawa	[27]
7	Kozo Kinoshita	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
8	Shin-ya Kobayashi	[15] [16] [17] [18] [23] [25] [30]
9	Kyohei Ono	[28]
10	Junichi Ootsu	[28]
11	Marong Phadoongsidhi	[14]
12	Irith Pomeranz	[17] [23]
13	Kewal K. Saluja	[6] [7] [8] [9] [10] [12] [14] [25] [26] [30]
14	Yasuo Sato	[24] [29]
15	Yuichi Sato	[19]
16	T. Seiyama	[22]
17	Hiroshi Takahashi	[14] [19] [20] [22] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33]
18	Naoko Takahashi	[13]
19	Yuzo Takamatsu	[8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33]
20	Toshiyuki Tsutsumi	[32] [33]
21	Yukihiro Yamamoto	[20]
22	Kazuo Yamazaki	[22]
23	Koji Yamazaki	[24] [29] [31] [32] [33]
24	Hiroyuki Yotsuyanagi	[27] [32] [33]