| 2006 |
|---|
| 5 | EE | S. H. Rasouli,
A. Amirabadi,
A. Seyedi,
Ali Afzali-Kusha:
Double edge triggered Feedback Flip-Flop in sub 100NM technology.
ASP-DAC 2006: 297-302 |
| 4 | EE | A. Amirabadi,
A. Chehelcheraghi,
S. H. Rasouli,
A. Seyedi,
Ali Afzali-Kusha:
Low power and high performance clock delayed domino logic using saturated keeper.
ISCAS 2006 |
| 3 | EE | A. S. Seyedi,
S. H. Rasouli,
A. Amirabadi,
Ali Afzali-Kusha:
Low power low leakage clock gated static pulsed flip-flop.
ISCAS 2006 |
| 2 | EE | A. S. Seyedi,
S. H. Rasouli,
A. Amirabadi,
Ali Afzali-Kusha:
Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology.
ISVLSI 2006: 373-377 |
| 2003 |
|---|
| 1 | EE | Ali Abbasian,
S. H. Rasouli,
Ali Afzali-Kusha,
Mehrdad Nourani:
No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications.
ISCAS (5) 2003: 289-292 |
