2009 |
29 | EE | Rosemary M. Francis,
Simon W. Moore:
FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis.
FPGA 2009: 285 |
2008 |
28 | EE | Rosemary M. Francis,
Simon W. Moore,
Robert D. Mullins:
A Network of Time-Division Multiplexed Wiring for FPGAs.
NOCS 2008: 35-44 |
27 | EE | Simon W. Moore,
Daniel Greenfield:
The next resource war: computation vs. communication.
SLIP 2008: 81-86 |
26 | EE | Daniel Greenfield,
Simon W. Moore:
Fractal communication in software data dependency graphs.
SPAA 2008: 116-118 |
2007 |
25 | EE | Robert D. Mullins,
Simon W. Moore:
Demystifying Data-Driven and Pausible Clocking Schemes.
ASYNC 2007: 175-185 |
24 | EE | Arnab Banerjee,
Robert D. Mullins,
Simon W. Moore:
A Power and Energy Exploration of Network-on-Chip Architectures.
NOCS 2007: 163-172 |
23 | EE | Daniel Greenfield,
Arnab Banerjee,
Jeong-Gun Lee,
Simon W. Moore:
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance.
NOCS 2007: 283-294 |
2006 |
22 | EE | Kate Taylor,
Simon W. Moore:
My Compiler Really Understands Me: An Adaptive Programming Language Tutor.
AH 2006: 389-392 |
21 | EE | Robert D. Mullins,
Andrew West,
Simon W. Moore:
The design and implementation of a low-latency on-chip network.
ASP-DAC 2006: 164-169 |
20 | EE | Petros Oikonomakos,
Jacques J. A. Fournier,
Simon W. Moore:
Implementing Cryptography on TFT Technology for Secure Display Applications.
CARDIS 2006: 32-47 |
19 | EE | Petros Oikonomakos,
Simon W. Moore:
An Asynchronous PLA with Improved Security Characteristics.
DSD 2006: 257-264 |
18 | EE | Jacques J. A. Fournier,
Simon W. Moore:
Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography.
DSD 2006: 439-446 |
17 | EE | Simon Hollis,
Simon W. Moore:
RasP: An Area-efficient, On-chip Network.
ICCD 2006 |
16 | EE | Simon Hollis,
Simon W. Moore:
An area-efficient, pulse-based interconnect.
ISCAS 2006 |
15 | EE | Simon Hollis,
Simon W. Moore:
An Asynchronous Interconnect Architecture for Device Security Enhancement.
VLSI Design 2006: 209-215 |
2005 |
14 | EE | Scott Fairbanks,
Simon W. Moore:
Self-Timed Circuitry for Global Clocking.
ASYNC 2005: 86-96 |
13 | EE | Huiyun Li,
A. Theodore Markettos,
Simon W. Moore:
Security Evaluation Against Electromagnetic Analysis at Design Time.
CHES 2005: 280-292 |
12 | EE | Jacques J. A. Fournier,
Simon W. Moore:
A Vector Approach to Cryptography Implementation.
DRMTICS 2005: 277-297 |
2004 |
11 | EE | Scott Fairbanks,
Simon W. Moore:
Analog Micropipeline Rings for High Precision Timing.
ASYNC 2004: 41-50 |
10 | EE | Robert D. Mullins,
Andrew West,
Simon W. Moore:
Low-Latency Virtual-Channel Routers for On-Chip Networks.
ISCA 2004: 188-197 |
2003 |
9 | EE | Jacques J. A. Fournier,
Simon W. Moore,
Huiyun Li,
Robert D. Mullins,
George S. Taylor:
Security Evaluation of Asynchronous Circuits.
CHES 2003: 137-151 |
8 | EE | Simon W. Moore,
Ross J. Anderson,
Robert D. Mullins,
George S. Taylor,
Jacques J. A. Fournier:
Balanced self-checking asynchronous logic for smart card applications.
Microprocessors and Microsystems 27(9): 421-430 (2003) |
2002 |
7 | EE | Simon W. Moore,
Robert D. Mullins,
Paul A. Cunningham,
Ross J. Anderson,
George S. Taylor:
Improving Smart Card Security Using Self-Timed Circuits.
ASYNC 2002: 211- |
6 | EE | George S. Taylor,
Simon W. Moore,
Robert D. Mullins,
Peter Robinson:
Point to Point GALS Interconnect.
ASYNC 2002: 69-75 |
5 | EE | Panit Watcharawitch,
Simon W. Moore:
JMA: The Java-Multithreading Architecture for Embedded Processors.
ICCD 2002: 527- |
2001 |
4 | EE | Simon W. Moore:
Protecting Consumer Security Devices.
E-smart 2001: 1 |
2000 |
3 | EE | George S. Taylor,
Simon W. Moore,
Steve Wilcox,
Peter Robinson:
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems.
ASYNC 2000: 45-51 |
2 | EE | Simon W. Moore,
George S. Taylor,
Paul A. Cunningham,
Robert D. Mullins,
Peter Robinson:
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems.
ICCD 2000: 73- |
1995 |
1 | | Simon W. Moore,
Brian T. Graham:
Tagged Up/Down Sorter - A Hardware Priority Queue.
Comput. J. 38(9): 695-703 (1995) |