| 2008 |
|---|
| 5 | EE | Zaher S. Andraus,
Mark H. Liffiton,
Karem A. Sakallah:
Reveal: A Formal Verification Tool for Verilog Designs.
LPAR 2008: 343-352 |
| 2006 |
|---|
| 4 | EE | Zaher S. Andraus,
Mark H. Liffiton,
Karem A. Sakallah:
Refinement strategies for verification methods based on datapath abstraction.
ASP-DAC 2006: 19-24 |
| 2005 |
|---|
| 3 | EE | Maher N. Mneimneh,
Inês Lynce,
Zaher S. Andraus,
João P. Marques Silva,
Karem A. Sakallah:
A Branch-and-Bound Algorithm for Extracting Smallest Minimal Unsatisfiable Formulas.
SAT 2005: 467-474 |
| 2004 |
|---|
| 2 | EE | Zaher S. Andraus,
Karem A. Sakallah:
Automatic abstraction and verification of verilog models.
DAC 2004: 218-223 |
| 1 | EE | Yoonna Oh,
Maher N. Mneimneh,
Zaher S. Andraus,
Karem A. Sakallah,
Igor L. Markov:
AMUSE: a minimally-unsatisfiable subformula extractor.
DAC 2004: 518-523 |
