Rung-Bin Lin

2008
29	EE	Wei-Chiu Tseng, Yu-Hsing Chen, Rung-Bin Lin: Router and cell library co-development for improving redundant via insertion at pins. ICCD 2008: 646-651
28	EE	Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Rung-Bin Lin: Standard Cell Like Via-Configurable Logic Block for Structured ASICs. ISVLSI 2008: 381-386
27	EE	Meng-Chiou Wu, Rung-Bin Lin, Shih-Cheng Tsai: Chip placement in a reticle for multiple-project wafer fabrication. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
26	EE	Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin: Power Reduction during Scan Testing Based on Multiple Capture Technique. IEICE Transactions 91-C(5): 798-805 (2008)
25	EE	Meng-Chiou Wu, Rung-Bin Lin: Finding Dicing Plans for Multiple Project wafers fabricated with Shuttle Mask. Journal of Circuits, Systems, and Computers 17(1): 15-31 (2008)
2007
24	EE	Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin: Double-via-driven standard cell library design. DATE 2007: 1212-1217
23		Rung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu: Reticle Exposure Plans for Multi-Project Wafers. DDECS 2007: 341-344
22	EE	Rung-Bin Lin, Shuyu Chen: Conjugate conflict continuation graphs for multi-layer constrained via minimization. Inf. Sci. 177(12): 2436-2447 (2007)
2006
21	EE	Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai: Design space exploration for minimizing multi-project wafer production cost. ASP-DAC 2006: 783-788
20	EE	Hsun-Chieh Yu, Rung-Bin Lin: Is more redundancy better for on-chip bus encoding. ISCAS 2006
2005
19	EE	Meng-Chiou Wu, Rung-Bin Lin: Reticle floorplanning of flexible chips for multi-project wafers. ACM Great Lakes Symposium on VLSI 2005: 494-497
18	EE	Guang-Wan Liao, Ja-Shong Feng, Rung-Bin Lin: A divide-and-conquer approach to estimating minimum/maximum leakage current. ISCAS (5) 2005: 4717-4720
17	EE	Meng-Chiou Wu, Rung-Bin Lin: Multiple project wafers for medium-volume IC production. ISCAS (5) 2005: 4725-4728
16	EE	Rung-Bin Lin: Coupling reduction analysis of bus-invert coding. ISCAS (6) 2005: 5862-5865
15	EE	Meng-Chiou Wu, Rung-Bin Lin: Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers. ISQED 2005: 610-615
14	EE	Meng-Chiou Wu, Rung-Bin Lin: A Comparative Study on Dicing of Multiple Project Wafers. ISVLSI 2005: 314-315
2004
13		Rung-Bin Lin, Shuyu Chen: Multi-layer constrained via minimization with conjugate conflict continuation graphs. ISCAS (4) 2004: 525-528
2003
12	EE	Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin: A Low Power-Delay Product Page-Based Address Bus Coding Method. VLSI Design 2003: 521-526
2002
11	EE	Rung-Bin Lin, Chi-Ming Tsai: Weight-Based Bus-Invert Coding for Low-Power Applications. VLSI Design 2002: 121-125
10	EE	Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin: An Adaptive Interconnect-Length Driven Placer. VLSI Design 2002: 393-398
9	EE	Rung-Bin Lin, Chi-Ming Tsai: Theoretical analysis of bus-invert coding. IEEE Trans. VLSI Syst. 10(6): 929-934 (2002)
8	EE	Rung-Bin Lin: Comments on "Filling algorithms and analyses for layout density control". IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1209-1211 (2002)
1999
7	EE	Rung-Bin Lin, Jinq-Chang Chen: Low Power CMOS Off-Chip Drivers with Slew-rate Difference. ASP-DAC 1999: 169-172
6	EE	Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai: Benchmark Circuits Improve the Quality of a Standard Cell Library. ASP-DAC 1999: 173-176
1998
5	EE	Rung-Bin Lin, Meng-Chiou Wu: A New Statistical Approach to Timing Analysis of VLSI Circuits. VLSI Design 1998: 507-
1994
4	EE	Eric Q. Kang, Rung-Bin Lin, Eugene Shragowitz: Fuzzy logic approach to VLSI placement. IEEE Trans. VLSI Syst. 2(4): 489-501 (1994)
1993
3	EE	Suphachai Sutanthavibul, Eugene Shragowitz, Rung-Bin Lin: An adaptive timing-driven placement for high performance VLSIs. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1488-1498 (1993)
1992
2	EE	Rung-Bin Lin, Eugene Shragowitz: Fuzzy Logic Approach to Placement Problem. DAC 1992: 153-158
1991
1		Habib Youssef, Rung-Bin Lin, Eugene Shragowitz: Bounds on Net Delays for Physical Design of Fast Circuits. VLSI 1991: 111-118

Coauthor Index

1	Jinq-Chang Chen	[7]
2	Shuyu Chen	[13] [22]
3	Yu-Hsing Chen	[29]
4	Isaac Shuo-Hsiu Chou	[6]
5	Ja-Shong Feng	[18]
6	Chyi-Hui Hong	[10]
7	Da-Wei Hsu	[23]
8	Eric Q. Kang	[4]
9	Kun-Tien Kuo	[10]
10	Ming-Hsine Kuo	[21] [23]
11	Chien-Chung Lai	[28]
12	Lung-Jen Lee	[26]
13	Mei-Chen Li	[28]
14	Guang-Wan Liao	[12] [18]
15	Tsai-Ying Lin	[21] [24]
16	Tsung-Han Lin	[24]
17	Eugene Shragowitz	[1] [2] [3] [4]
18	Suphachai Sutanthavibul	[3]
19	Chi-Ming Tsai	[6] [9] [10] [11] [12]
20	Shih-Cheng Tsai	[27]
21	Shr-Cheng Tsai	[21]
22	Wang-Dauh Tseng	[26]
23	Wei-Chiu Tseng	[21] [29]
24	Hui-Hsiang Tung	[24] [28]
25	Meng-Chiou Wu	[5] [14] [15] [17] [19] [21] [23] [25] [27]
26	Habib Youssef	[1]
27	Hsun-Chieh Yu	[20]

Colors in the list of coauthors