| 2008 |
|---|
| 15 | EE | Yu-Han Chen,
Tung-Chien Chen,
Chuan-Yung Tsai,
Sung-Fang Tsai,
Liang-Gee Chen:
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder.
Signal Processing Systems 50(1): 1-17 (2008) |
| 14 | EE | Yi-Hau Chen,
Tung-Chien Chen,
Shao-Yi Chien,
Yu-Wen Huang,
Liang-Gee Chen:
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC.
Signal Processing Systems 53(3): 335-347 (2008) |
| 2007 |
|---|
| 13 | EE | Pei-Kuei Tsung,
Li-Fu Ding,
Wei-Yin Chen,
Shao-Yi Chien,
Tung-Chien Chen,
Liang-Gee Chen:
System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint.
ISCAS 2007: 1001-1004 |
| 12 | EE | Tung-Chien Chen,
Chuan-Yung Tsai,
Yu-Wen Huang,
Liang-Gee Chen:
Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC.
IEEE Trans. Circuits Syst. Video Techn. 17(2): 242-247 (2007) |
| 2006 |
|---|
| 11 | EE | Tung-Chien Chen,
Chung-Jr Lian,
Liang-Gee Chen:
Hardware architecture design of an H.264/AVC video codec.
ASP-DAC 2006: 750-757 |
| 10 | EE | Chuan-Yung Tsai,
Tung-Chien Chen,
Liang-Gee Chen:
Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder.
ICME 2006: 1941-1944 |
| 9 | EE | Yu-Han Chen,
Tung-Chien Chen,
Liang-Gee Chen:
Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application.
ICME 2006: 281-284 |
| 8 | EE | Tung-Chien Chen,
Yu-Han Chen,
Chuan-Yung Tsai,
Liang-Gee Chen:
Low power and power aware fractional motion estimation of H.264/AVC for mobile applications.
ISCAS 2006 |
| 7 | EE | Tung-Chien Chen,
Shao-Yi Chien,
Yu-Wen Huang,
Chen-Han Tsai,
Ching-Yeh Chen,
To-Wei Chen,
Liang-Gee Chen:
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder.
IEEE Trans. Circuits Syst. Video Techn. 16(6): 673-688 (2006) |
| 2005 |
|---|
| 6 | EE | Tung-Chien Chen,
Yu-Wen Huang,
Chuan-Yung Tsai,
Chao-Tsung Huang,
Liang-Gee Chen:
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC.
ISCAS (2) 2005: 1790-1793 |
| 5 | EE | To-Wei Chen,
Yu-Wen Huang,
Tung-Chien Chen,
Yu-Han Chen,
Chuan-Yung Tsai,
Liang-Gee Chen:
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos.
ISCAS (3) 2005: 2931-2934 |
| 4 | EE | Yu-Wen Huang,
Bing-Yu Hsieh,
Tung-Chien Chen,
Liang-Gee Chen:
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder.
IEEE Trans. Circuits Syst. Video Techn. 15(3): 378-401 (2005) |
| 2004 |
|---|
| 3 | | Yu-Wen Huang,
Bing-Yu Hsieh,
Tung-Chien Chen,
Liang-Gee Chen:
Hardware architecture design for H.264/AVC intra frame coder.
ISCAS (2) 2004: 269-272 |
| 2 | | Tung-Chien Chen,
Yu-Wen Huang,
Liang-Gee Chen:
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture.
ISCAS (2) 2004: 273-276 |
| 2003 |
|---|
| 1 | EE | Wei-Min Chao,
Tung-Chien Chen,
Yung-Chi Chang,
Chih-Wei Hsu,
Liang-Gee Chen:
Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 Advanced Simple Profile.
ISCAS (2) 2003: 788-791 |
