Hortensia Mecha

2008
17		Angel Luis González Bravo, Hortensia Mecha, Julio Septién, Sara Román Navarro, Daniel Mozos: Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system. ERSA 2008: 307-308
16		Laura Sanchez, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo: FPGA Resource Management Using Internal RAM as Aata Cache. ERSA 2008: 317-318
15		Jose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo: Resource Management for Hw Multitasking in Three Dimensional FPGAs. ERSA 2008: 319-320
14	EE	Julio Septién, Daniel Mozos, Hortensia Mecha, Jesús Tabero, Miguel Angel García de Dios: Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking. IPDPS 2008: 1-8
13	EE	Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos: Allocation heuristics and defragmentation measures for reconfigurable systems management. Integration 41(2): 281-296 (2008)
2006
12	EE	Sara Román Navarro, Julio Septién, Hortensia Mecha, Daniel Mozos: Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs. ARC 2006: 187-192
11	EE	Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos: Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. ASP-DAC 2006: 396-401
10	EE	Sara Román Navarro, Hortensia Mecha, Daniel Mozos, Julio Septién: Partition Based Dynamic 2D HW Multitasking Management. DSD 2006: 61-70
9	EE	Julio Septién, Hortensia Mecha, Daniel Mozos, Jesús Tabero: 2D defragmentation heuristics for hardware multitasking on reconfigurable devices. IPDPS 2006
2004
8	EE	Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos: A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management. FPL 2004: 241-250
2003
7	EE	Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién: A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. PATMOS 2003: 580-589
6	EE	Javier Resano, M. Elena Pérez, Daniel Mozos, Hortensia Mecha, Julio Septién: Analyzing communication overheads during hardware/software partitioning. Microelectronics Journal 34(11): 1001-1007 (2003)
1999
5	EE	Katzalin Olcoz, Francisco Tirado, Hortensia Mecha: Unified data path allocation and BIST intrusion. Integration 28(1): 55-99 (1999)
1998
4	EE	J. A. Maestro, Daniel Mozos, Hortensia Mecha: A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process. DATE 1998: 218-225
1997
3	EE	Hortensia Mecha, Milagros Fernández: Interconnection Delay and Clock Cycle Selection in High Level Synthesis. VLSI Design 1997: 504-505
2	EE	R. Moreno, Román Hermida, Milagros Fernández, Hortensia Mecha: A unified approach for scheduling and allocation. Integration 23(1): 1-35 (1997)
1996
1	EE	Hortensia Mecha, Milagros Fernández, Francisco Tirado, Julio Septién, D. Motes, Katzalin Olcoz: A method for area estimation of data-path in high level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 258-265 (1996)

Coauthor Index

1	Angel Luis González Bravo	[15] [16] [17]
2	Miguel Angel García de Dios	[14]
3	Milagros Fernández	[1] [2] [3]
4	Román Hermida	[2]
5	J. A. Maestro	[4]
6	R. Moreno	[2]
7	D. Motes	[1]
8	Daniel Mozos	[4] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
9	Sara Román Navarro	[10] [12] [17]
10	Katzalin Olcoz	[1] [5]
11	M. Elena Pérez	[6]
12	Elena Pérez-Miñana	[7]
13	Javier Resano	[6] [7]
14	Laura Sanchez	[16]
15	Julio Septién	[1] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
16	Jesús Tabero	[8] [9] [11] [13] [14]
17	Francisco Tirado	[1] [5]
18	Jose Antonio Valero	[15]