2008 |
21 | EE | Shih-Hao Ou,
Tay-Jyi Lin,
Xiang Sheng Deng,
Zhi Hong Zhuo,
Chih-Wei Liu:
Multithreaded coprocessor interface for multi-core multimedia SoC.
ASP-DAC 2008: 115-116 |
20 | EE | Jwo-An Lin,
Yung-Chou Tsai,
Tay-Jyi Lin,
Yarsun Hsu:
Cycle Stealing and Channel Management for On-Chip Networks.
HPCC 2008: 53-60 |
19 | EE | Yu-Ting Kuo,
Tay-Jyi Lin,
Wei-Han Chang,
Yueh-Tai Li,
Chih-Wei Liu,
Shuenn-Tsong Young:
Complexity-effective auditory compensation for digital hearing aids.
ISCAS 2008: 1472-1475 |
18 | EE | Shih-Hao Ou,
Yi Cho,
Tay-Jyi Lin,
Chih-Wei Liu:
Improving datapathutilization of programmable DSP with composite functional units.
ISCAS 2008: 3438-3441 |
17 | EE | Tay-Jyi Lin,
Shin-Kai Chen,
Yu-Ting Kuo,
Chih-Wei Liu,
Pi-Chen Hsiao:
Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications.
Signal Processing Systems 51(3): 209-223 (2008) |
2007 |
16 | EE | Li-Chun Lin,
Shih-Hao Ou,
Tay-Jyi Lin,
Siang-Den Deng,
Chih-Wei Liu:
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes.
ASP-DAC 2007: 110-111 |
15 | EE | Pi-Chen Hsiao,
Tay-Jyi Lin,
Chih-Wei Liu,
Chein-Wei Jen:
Latency-Tolerant Virtual Cluster Architecture for VLIW DSP.
ISCAS 2007: 3506-3509 |
14 | EE | Shin-Kai Chen,
Bing-Shiun Wang,
Tay-Jyi Lin,
Chih-Wei Liu:
Rapid C to FPGA Prototyping with Multithreaded Emulation Engine.
ISCAS 2007: 409-412 |
2006 |
13 | EE | Shih-Hao Ou,
Tay-Jyi Lin,
Chao-Wei Huang,
Yu-Ting Kuo,
Chie-Min Chao,
Chih-Wei Liu,
Chein-Wei Jen:
A 52mW 1200MIPS compact DSP for multi-core media SoC.
ASP-DAC 2006: 118-119 |
12 | EE | Yu-Ting Kuo,
Tay-Jyi Lin,
Yi Cho,
Chih-Wei Liu,
Chein-Wei Jen:
Programmable FIR filter with adder-based computing engine.
ISCAS 2006 |
11 | EE | Tay-Jyi Lin,
Hung-Yueh Lin,
Chie-Min Chao,
Chih-Wei Liu,
Chih-Wei Jen:
A Compact DSP Core with Static Floating-Point Arithmetic.
VLSI Signal Processing 42(2): 127-138 (2006) |
2005 |
10 | EE | Tay-Jyi Lin,
Chie-Min Chao,
Chia-Hsien Liu,
Pi-Chen Hsiao,
Shin-Kai Chen,
Li-Chun Lin,
Chih-Wei Liu,
Chein-Wei Jen:
A unified processor architecture for RISC & VLIW DSP.
ACM Great Lakes Symposium on VLSI 2005: 50-55 |
9 | EE | Yu-Ting Kuo,
Tay-Jyi Lin,
Chih-Wei Liu,
Chein-Wei Jen:
Architecture for area-efficient 2-D transform in H.264/AVC.
ICME 2005: 1126-1129 |
8 | EE | Wei-Sheng Huang,
Tay-Jyi Lin,
Shih-Hao Ou,
Chih-Wei Liu,
Chein-Wei Jen:
Pipelining technique for energy-aware datapaths.
ISCAS (2) 2005: 1218-1221 |
7 | EE | Chia-Hsien Liu,
Tay-Jyi Lin,
Chie-Min Chao,
Pi-Chen Hsiao,
Li-Chun Lin,
Shin-Kai Chen,
Chao-Wei Huang,
Chih-Wei Liu,
Chein-Wei Jen:
Hierarchical instruction encoding for VLIW digital signal processors.
ISCAS (4) 2005: 3503-3506 |
2004 |
6 | EE | Tay-Jyi Lin,
Hung-Yueh Lin,
Chie-Min Chao,
Chih-Wei Liu,
Chein-Wei Jen:
A compact DSP core with static floating-point unit & its microcode generation.
ACM Great Lakes Symposium on VLSI 2004: 57-60 |
5 | | Hung-Yueh Lin,
Tay-Jyi Lin,
Chie-Min Chao,
Yen-Chin Liao,
Chih-Wei Liu,
Chein-Wei Jen:
Static floating-point unit with implicit exponent tracking for embedded DSP.
ISCAS (2) 2004: 821-824 |
2003 |
4 | EE | Tay-Jyi Lin,
Chin-Chi Chang,
Chen-Chia Lee,
Chein-Wei Jen:
An Efficient VLIW DSP Architecture for Baseband Processing.
ICCD 2003: 307-312 |
3 | EE | Tay-Jyi Lin,
Tsung-Hsun Yang,
Chein-Wei Jen:
Area-effective FIR filter design for multiplier-less implementation.
ISCAS (5) 2003: 173-176 |
2002 |
2 | EE | Tay-Jyi Lin,
Chein-Wei Jen:
CASCADE - configurable and scalable DSP environment.
ISCAS (4) 2002: 870-873 |
2001 |
1 | EE | Tay-Jyi Lin,
Chein-Wei Jen:
An efficient 2-D DWT architecture via resource cycling.
ISCAS (4) 2001: 914-917 |