| 2008 |
|---|
| 4 | EE | Kenta Yamada,
Noriaki Oda:
Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications).
IEICE Transactions 91-C(4): 562-570 (2008) |
| 2007 |
|---|
| 3 | EE | Noriaki Oda,
Hironori Imura,
Naoyoshi Kawahara,
Masayoshi Tagami,
Hiroyuki Kunishima,
Shuji Sone,
Sadayuki Ohnishi,
Kenta Yamada,
Yumi Kakuhara,
Makoto Sekine,
Yoshihiro Hayashi,
Kazuyoshi Ueno:
Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation.
IEICE Transactions 90-C(4): 848-855 (2007) |
| 2006 |
|---|
| 2 | EE | Kenta Yamada,
Noriaki Oda:
Statistical corner conditions of interconnect delay (corner LPE specifications).
ASP-DAC 2006: 706-711 |
| 1 | EE | Noriaki Oda,
Hiroyuki Kunishima,
Takashi Kyouno,
Kazuhiro Takeda,
Tomoaki Tanaka,
Toshiyuki Takewaki,
Masahiro Ikeda:
Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond.
IEICE Transactions 89-C(11): 1544-1550 (2006) |
