| 2008 |
|---|
| 54 | EE | Shinobu Nagayama,
Tsutomu Sasao,
Jon T. Butler:
Numerical function generators using bilinear interpolation.
FPL 2008: 463-466 |
| 2007 |
|---|
| 53 | EE | Shinobu Nagayama,
Tsutomu Sasao,
Jon T. Butler:
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams.
ASP-DAC 2007: 535-540 |
| 52 | EE | Shinobu Nagayama,
Tsutomu Sasao,
Jon T. Butler:
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation.
DSD 2007: 280-287 |
| 51 | EE | Tsutomu Sasao,
Shinobu Nagayama,
Jon T. Butler:
Numerical Function Generators Using LUT Cascades.
IEEE Trans. Computers 56(6): 826-838 (2007) |
| 50 | EE | Shinobu Nagayama,
Tsutomu Sasao,
Jon T. Butler:
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs.
IEICE Transactions 90-A(12): 2752-2761 (2007) |
| 2006 |
|---|
| 49 | EE | Hui Qin,
Tsutomu Sasao,
Jon T. Butler:
Implementation of LPM Address Generators on FPGAs.
ARC 2006: 170-181 |
| 48 | EE | Shinobu Nagayama,
Tsutomu Sasao,
Jon T. Butler:
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method.
ASP-DAC 2006: 378-383 |
| 47 | EE | Tsutomu Sasao,
Jon T. Butler:
Implementation of Multiple-Valued CAM Functions by LUT Cascades.
ISMVL 2006: 11 |
| 46 | EE | Shinobu Nagayama,
Tsutomu Sasao,
Jon T. Butler:
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method.
IEICE Transactions 89-A(12): 3510-3518 (2006) |
| 2005 |
|---|
| 45 | | Tsutomu Sasao,
Shinobu Nagayama,
Jon T. Butler:
Programmable Numerical Function Generators: Architectures and Synthesis Method.
FPL 2005: 118-123 |
| 44 | EE | Jon T. Butler,
Tsutomu Sasao,
Munehiro Matsuura:
Average Path Length of Binary Decision Diagrams.
IEEE Trans. Computers 54(9): 1041-1053 (2005) |
| 2004 |
|---|
| 43 | EE | Tsutomu Sasao,
Jon T. Butler:
A fast method to derive minimum SOPs for decomposable functions.
ASP-DAC 2004: 585-590 |
| 2003 |
|---|
| 42 | EE | Jon T. Butler,
Tsutomu Sasao:
On the Average Path Length in Decision Diagrams of Multiple-Valued Functions.
ISMVL 2003: 383-390 |
| 2001 |
|---|
| 41 | EE | Tsutomu Sasao,
Jon T. Butler:
On the minimization of SOPs for bi-decomposition functions.
ASP-DAC 2001: 219-224 |
| 40 | | Jon T. Butler,
Gerhard W. Dueck,
Svetlana N. Yanushkevich,
Vlad P. Shmerko:
On the number of generators for transeunt triangles.
Discrete Applied Mathematics 108(3): 309-316 (2001) |
| 39 | EE | Tsutomu Sasao,
Jon T. Butler:
Worst and Best Irredundant Sum-of-Products Expressions.
IEEE Trans. Computers 50(9): 935-948 (2001) |
| 2000 |
|---|
| 38 | EE | Svetlana N. Yanushkevich,
Jon T. Butler,
Gerhard W. Dueck,
Vlad P. Shmerko:
Experiments on FPRM Expressions for Partially Symmetric Logic Functions.
ISMVL 2000: 141-146 |
| 37 | EE | Jon T. Butler,
Gerhard W. Dueck,
Vlad P. Shmerko,
Svetlana N. Yanushkevich:
Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions".
IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1386-1388 (2000) |
| 1998 |
|---|
| 36 | EE | Jon T. Butler,
Tsutomu Sasao:
On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels.
ISMVL 1998: 83-88 |
| 1997 |
|---|
| 35 | EE | Tsutomu Sasao,
Jon T. Butler:
Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions.
ISMVL 1997: 55-60 |
| 34 | | Kriss A. Schueller,
Jon T. Butler:
Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits.
IEEE Trans. Computers 46(2): 205-209 (1997) |
| 33 | | Jon T. Butler,
David S. Herscovici,
Tsutomu Sasao,
Robert J. Barton III:
Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions.
IEEE Trans. Computers 46(4): 491-494 (1997) |
| 1996 |
|---|
| 32 | EE | Jon T. Butler,
J. L. Nowlin,
Tsutomu Sasao:
Planarity in ROMDD's of Multiple-Valued Symmetric Functions.
ISMVL 1996: 236-241 |
| 31 | EE | Tsutomu Sasao,
Jon T. Butler:
A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams.
ISMVL 1996: 248-254 |
| 1995 |
|---|
| 30 | EE | Tsutomu Sasao,
Jon T. Butler:
Planar Multiple-Valued Decision Diagrams.
ISMVL 1995: 28-35 |
| 1994 |
|---|
| 29 | | Jon T. Butler,
Tsutomu Sasao:
Multiple-Valued Combinational Circuits with Feedback.
ISMVL 1994: 342-347 |
| 28 | | Gerhard W. Dueck,
Jon T. Butler:
Multiple-Valued Logic Operations with Universal Literals.
ISMVL 1994: 73-79 |
| 27 | | Tsutomu Sasao,
Jon T. Butler:
A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion.
ISMVL 1994: 97-106 |
| 1993 |
|---|
| 26 | | Cem Yildirim,
Jon T. Butler,
Chyan Yang:
Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing.
ISMVL 1993: 17-23 |
| 1992 |
|---|
| 25 | | Susan W. Butler,
Jon T. Butler:
Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991.
ISMVL 1992: 372-379 |
| 24 | | Gerhard W. Dueck,
Robert C. Earle,
Parthasarathy P. Tirumalai,
Jon T. Butler:
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing.
ISMVL 1992: 66-74 |
| 23 | | Kriss A. Schueller,
Jon T. Butler:
On the Design of Cost-Tables for Realizing Multiple-Valued Circuits.
IEEE Trans. Computers 41(2): 178-189 (1992) |
| 1991 |
|---|
| 22 | | Young-hoon Chang,
Jon T. Butler:
The Design of Current Mode CMOS Multiple-Valued Circuits.
ISMVL 1991: 130-138 |
| 21 | | Jon T. Butler,
Kriss A. Schueller:
Worst Case Number of Terms in Symmetric Multiple-Valued Functions.
ISMVL 1991: 94-101 |
| 20 | | Parthasarathy P. Tirumalai,
Jon T. Butler:
Minimization Algorithms for Multiple-Valued Programmable Logic Arrays.
IEEE Trans. Computers 40(2): 167-177 (1991) |
| 1990 |
|---|
| 19 | | John M. Yurchak,
Jon T. Butler:
HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays.
ISMVL 1990: 144-152 |
| 18 | | Jon T. Butler,
Hans G. Kerkhoff,
Siep Onneweer:
A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach.
ISMVL 1990: 286-291 |
| 17 | | Joo-Kang Lee,
Jon T. Butler:
A Characterization of t/s-Diagnosability an Sequential t-Diagnosability in Designs.
IEEE Trans. Computers 39(10): 1298-1304 (1990) |
| 16 | | Jon T. Butler,
Kriss A. Schueller:
On the Equivalence of Cost Functions in the Design of Circuits by Costtable.
IEEE Trans. Computers 39(6): 842-844 (1990) |
| 1989 |
|---|
| 15 | | Edward A. Bender,
Jon T. Butler:
On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions.
IEEE Trans. Computers 38(1): 82-98 (1989) |
| 1988 |
|---|
| 14 | | Jon T. Butler:
Multiple-Valued Logic - Guest Editor's Introduction.
IEEE Computer 21(4): 13-15 (1988) |
| 13 | | Jon T. Butler,
Hans G. Kerkhoff:
Multiple-Valued CCD Circuits.
IEEE Computer 21(4): 58-69 (1988) |
| 1985 |
|---|
| 12 | EE | Edward A. Bender,
Jon T. Butler:
Enumeration of Structured Flowcharts
J. ACM 32(3): 537-548 (1985) |
| 1982 |
|---|
| 11 | EE | Jon T. Butler:
On the relationship between propagating context-dependent lindenmayer systems and cellular automata systems.
Inf. Sci. 28(1): 63-67 (1982) |
| 1981 |
|---|
| 10 | | Jon T. Butler:
Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms.
IEEE Trans. Computers 30(8): 590-596 (1981) |
| 1980 |
|---|
| 9 | | Patrick E. White,
Jon T. Butler:
Synthesis of One-Dimensional Binary Scope-2 Flexible Cellular Systems from Initial Final Configuration Pairs
Information and Control 46(3): 241-256 (1980) |
| 1979 |
|---|
| 8 | | Jon T. Butler:
Synthesis of One-Dimensional Binary Cellular Automata Systems from Composite Local Maps
Information and Control 43(3): 304-326 (1979) |
| 7 | | Jon T. Butler:
Decomposable Maps in General Tessellation Structures.
J. Comput. Syst. Sci. 18(1): 1-7 (1979) |
| 1978 |
|---|
| 6 | | Edward A. Bender,
Jon T. Butler:
Asymptotic Aproximations for the Number of Fanout-Free Functions.
IEEE Trans. Computers 27(12): 1180-1183 (1978) |
| 5 | | Jon T. Butler:
Tandem Networks of Universal Cells.
IEEE Trans. Computers 27(9): 785-799 (1978) |
| 4 | EE | Jon T. Butler:
Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates.
J. ACM 25(3): 481-498 (1978) |
| 1976 |
|---|
| 3 | | Jon T. Butler:
Restricted Cellular Networks.
IEEE Trans. Computers 25(11): 1139-1142 (1976) |
| 1975 |
|---|
| 2 | | Jon T. Butler:
On the Number of Functions Realized by Cascades and Disjunctive Networks.
IEEE Trans. Computers 24(7): 681-690 (1975) |
| 1974 |
|---|
| 1 | | Jon T. Butler:
A Note on Cellular Automata Simulations
Information and Control 26(3): 286-295 (1974) |
