Jeng-Liang Tsai

2006
12	EE	Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen: Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. ASP-DAC 2006: 941-946
11	EE	Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen: Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. ISCAS 2006
2005
10	EE	Jeng-Liang Tsai, Charlie Chung-Ping Chen: Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. ASP-DAC 2005: 1168-1171
9		Jeng-Liang Tsai, Lizheng Zhang: Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. ICCAD 2005: 575-581
8	EE	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja: False Path and Clock Scheduling Based Yield-Aware Gate Sizing. VLSI Design 2005: 423-426
7	EE	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja: Yield-Driven, False-Path-Aware Clock Skew Scheduling. IEEE Design & Test of Computers 22(3): 214-222 (2005)
2004
6	EE	Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen: Thermal and Power Integrity Based Power/Ground Networks Optimization. DATE 2004: 830-835
5	EE	Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik: HiSIM: hierarchical interconnect-centric circuit simulator. ICCAD 2004: 489-496
4	EE	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja: A yield improvement methodology using pre- and post-silicon statistical clock scheduling. ICCAD 2004: 611-618
3	EE	Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen: Sensitivity guided net weighting for placement driven synthesis. ISPD 2004: 124-131
2	EE	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen: Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 565-572 (2004)
2003
1	EE	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen: Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. ISPD 2003: 166-173

Coauthor Index

1	Dong Hyun Baik	[4] [7] [8]
2	Charlie Chung-Ping Chen (Chung-Ping Chen)	[1] [2] [3] [4] [6] [7] [8] [10] [11] [12]
3	Tsung-Hao Chen	[1] [2] [5]
4	Weijen Chen	[12]
5	Yuhen Hu	[12]
6	Pei-Yu Huang	[11]
7	Tanay Karnik	[5]
8	Yu-Min Lee	[11]
9	Kewal K. Saluja	[4] [7] [8]
10	Ting-Yuan Wang	[3] [6]
11	Lizheng Zhang	[9] [12]