2006 |
6 | EE | Dac Pham,
Hans-Werner Anderson,
Erwin Behnen,
Mark Bolliger,
Sanjay Gupta,
H. Peter Hofstee,
Paul E. Harvey,
Charles R. Johns,
James A. Kahle,
Atsushi Kameyama,
John M. Keaty,
Bob Le,
Sang Lee,
Tuyen V. Nguyen,
John G. Petrovick,
Mydung Pham,
Juergen Pille,
Stephen D. Posluszny,
Mack W. Riley,
Joseph Verock,
James D. Warnock,
Steve Weitzel,
Dieter F. Wendel:
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.
ASP-DAC 2006: 871-878 |
2002 |
5 | EE | James D. Warnock,
John M. Keaty,
John G. Petrovick,
Joachim G. Clabes,
Charles J. Kircher,
Byron Krauter,
Phillip Restle,
Brian A. Zoric,
Carl J. Anderson:
The circuit and physical design of the POWER4 microprocessor.
IBM Journal of Research and Development 46(1): 27-52 (2002) |
1997 |
4 | EE | A. Bertolet,
K. Carpenter,
Keith M. Carrig,
Albert M. Chu,
A. Dean,
Frank D. Ferraiolo,
S. Kenyon,
D. Phan,
John G. Petrovick,
G. Rodgers,
D. Willmott,
T. Bairley,
T. Decker,
V. Girardi,
Y. Lapid,
M. Murphy,
P. Andrew Scott,
Richard J. Weiss:
A pseudo-hierarchical methodology for high performance microprocessor design.
ISPD 1997: 124-129 |
3 | EE | Keith M. Carrig,
Albert M. Chu,
Frank D. Ferraiolo,
John G. Petrovick,
P. Andrew Scott,
Richard J. Weiss:
A Clock Methodology for High-Performance Microprocessors.
VLSI Signal Processing 16(2-3): 217-224 (1997) |
1990 |
2 | EE | Robert W. Bassett,
Barry J. Butkus,
Stephen L. Dingle,
Marc R. Faucher,
Pamela S. Gillis,
Jeannie H. Panner,
John G. Petrovick,
Donald L. Wheater:
Low-Cost Testing of High-Density Logic Components.
IEEE Design & Test of Computers 7(2): 15-28 (1990) |
1989 |
1 | | Robert W. Bassett,
Barry J. Butkus,
Stephen L. Dingle,
Marc R. Faucher,
Pamela S. Gillis,
Jeannie H. Panner,
John G. Petrovick,
Donald L. Wheater:
Low Cost Testing of High Density Logic Components.
ITC 1989: 550-557 |