| 2007 |
| 33 | EE | Masao Morimoto,
Makoto Nagata,
Kazuo Taki:
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations.
IEICE Transactions 90-C(4): 675-682 (2007) |
| 32 | EE | Yohei Fukumizu,
Naoki Gochi,
Makoto Nagata,
Kazuo Taki:
A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System.
IEICE Transactions 90-C(6): 1299-1303 (2007) |
| 2006 |
| 31 | EE | Mitsuya Fukazawa,
Koichiro Noguchi,
Makoto Nagata,
Kazuo Taki:
A built-in power supply noise probe for digital LSIs.
ASP-DAC 2006: 106-107 |
| 30 | EE | Yohei Fukumizu,
Shuji Ohno,
Makoto Nagata,
Kazuo Taki:
Communication Scheme for a Highly Collision-Resistive RFID System.
IEICE Transactions 89-A(2): 408-415 (2006) |
| 29 | EE | Yohei Fukumizu,
Makoto Nagata,
Kazuo Taki:
Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach.
IEICE Transactions 89-C(11): 1581-1590 (2006) |
| 2005 |
| 28 | EE | Masao Morimoto,
Yoshinori Tanaka,
Makoto Nagata,
Kazuo Taki:
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition.
IEICE Transactions 88-A(12): 3324-3331 (2005) |
| 27 | EE | Masao Morimoto,
Makoto Nagata,
Kazuo Taki:
High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition.
IEICE Transactions 88-C(10): 2001-2008 (2005) |
| 2003 |
| 26 | EE | Shuusuke Haruna,
Norio Sanada,
Hisayuki Kinoh,
Kazutoshi Sumiya,
Kazuo Taki:
A GUI software development system for digital AV applications.
Systems and Computers in Japan 34(7): 99-107 (2003) |
| 2000 |
| 25 | EE | Hirofumi Sakamoto,
Ken'ichiro Uda,
Bu-Y. Lee,
Hiroyuki Ochi,
Kazuo Taki,
Takao Tsuda:
A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL.
ASP-DAC 2000: 33-34 |
| 1999 |
| 24 | EE | Tsuyoshi Shinogi,
Terumine Hayashi,
Kazuo Taki:
Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits.
Systems and Computers in Japan 30(7): 55-68 (1999) |
| 1998 |
| 23 | | Kazuo Taki:
A Survey for Pass-Transistor Logic Technologies - Recent Researches and Developments and Future Prospects (Embedded Tutorial).
ASP-DAC 1998: 223-226 |
| 22 | EE | Masahiro Yasugi,
Shegeyuki Eguchi,
Kazuo Taki:
Eliminating Bottlenecks on Parallel Systems using Adaptive Objects.
IEEE PACT 1998: 80-87 |
| 1997 |
| 21 | EE | Tsuyoshi Shinogi,
Terumine Hayashi,
Kazuo Taki:
Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL.
Asian Test Symposium 1997: 16-21 |
| 1992 |
| 20 | | Kazuo Taki:
Towards the General-Purpose Parallel Processing System, Panel Position Paper.
FGCS 1992: 1074-1075 |
| 19 | | Yukinori Matsumoto,
Kazuo Taki:
Parallel Logic Simulator based on Time Warp and its Evaluation.
FGCS 1992: 1198-1206 |
| 18 | | Katsumi Nitta,
Kazuo Taki,
Nobuyuki Ichiyoshi:
Experimental Parallel Inference Software.
FGCS 1992: 166-190 |
| 17 | | Hiroshi Date,
Yukinori Matsumoto,
Kouichi Kimura,
Kazuo Taki,
Hiroo Kato,
Masahiro Hoshi:
LSI-CAD Programs on Parallel Inference Machine.
FGCS 1992: 237-247 |
| 16 | | Keiji Hirata,
Reki Yamamoto,
Akira Imai,
Hideo Kawai,
Kiyoshi Hirano,
Tsuneyoshi Takagi,
Kazuo Taki,
Akihiko Nakase,
Kazuaki Rokusawa:
Parallel and Distributed Implementation of Concurrent Logic Programming Language KL1.
FGCS 1992: 436-459 |
| 15 | | Kazuo Taki:
Parallel Inference Machine PIM.
FGCS 1992: 50-72 |
| 1991 |
| 14 | | Kazuo Taki:
Parallel Programming and Large-scale Applications in the FGCS Project.
ICLP 1991: 949 |
| 1990 |
| 13 | | Masakazu Furuichi,
Kazuo Taki,
Nobuyuki Ichiyoshi:
A Multi-Level Load Balancing Scheme for OR-Parallel Exhaustive Search Programs on the Multi-PSI.
PPOPP 1990: 50-59 |
| 1989 |
| 12 | | Kazuo Taki:
The FGCS Computing Architecture.
IFIP Congress 1989: 627-632 |
| 1988 |
| 11 | | Kanae Masuda,
Hirokazu Ishizuka,
Hiroaki Iwayama,
Kazuo Taki,
Eiji Sugino:
Preliminary Evaluation of the Connection Network for the Multi-PSI System.
ECAI 1988: 18-23 |
| 10 | | Shunichi Uchida,
Kazuo Taki,
Katsuto Nakajima,
Atsuhiro Goto,
Takashi Chikayama:
Research and Development of the Parallel Inference System in the Intermediate Stage of the FGCS Project.
FGCS 1988: 16-36 |
| 9 | | Atsuhiro Goto,
Masatoshi Sato,
Katsuto Nakajima,
Kazuo Taki,
Akira Matsumoto:
Overview of the Parallel Inference Machine Architecture (PIM).
FGCS 1988: 208-229 |
| 8 | | Yasutaka Takeda,
Hiroshi Nakashima,
Kanae Masuda,
Takashi Chikayama,
Kazuo Taki:
A Load Balancing Mechanism for Large Scale Multiprocessor Systems and its Implementation.
FGCS 1988: 978-986 |
| 1987 |
| 7 | | Kazuo Taki,
Katsuto Nakajima,
Hiroshi Nakashima,
Morihiro Ikeda:
Performance and Architectural Evaluation of the PSI Machine.
ASPLOS 1987: 128-135 |
| 6 | | M. Ichiyoshi,
T. Miyazaki,
Kazuo Taki:
A Distributed Implementation of Flat GHC on the Multi-PSI.
ICLP 1987: 257-275 |
| 1986 |
| 5 | | Katsuto Nakajima,
Hiroshi Nakashima,
Minoru Yokota,
Kazuo Taki,
Shunichi Uchida,
Hiroshi Nishikawa,
Akira Yamamoto,
Masaki Mitsui:
Evaluation of PSI Micro-Interpreter.
COMPCON 1986: 173-177 |
| 1984 |
| 4 | | Kazuo Taki,
Minoru Yokota,
Akira Yamamoto,
Hiroshi Nishikawa,
Shunichi Uchida,
Hiroshi Nakashima,
Akitoshi Mitsuishi:
Hardware Design and Implementation of the Personal Sequential Inference Machine (PSI).
FGCS 1984: 398-409 |
| 3 | | Minoru Yokota,
Akira Yamamoto,
Kazuo Taki,
Hiroshi Nishikawa,
Shunichi Uchida,
Katsuto Nakajima,
Masaki Mitsui:
A Microprogrammed Interpreter for the Personal Sequential Inference Machine.
FGCS 1984: 410-418 |
| 1983 |
| 2 | | Shunichi Uchida,
Minoru Yokota,
Akira Yamamoto,
Kazuo Taki,
Hiroshi Nishikawa:
Outline of the Personal Sequential Inference Machine: PSI.
New Generation Comput. 1(1): 75-79 (1983) |
| 1 | | Minoru Yokota,
Akira Yamamoto,
Kazuo Taki,
Hiroshi Nishikawa,
Shunichi Uchida:
The Design and Implementation of a Personal Sequential Inference Machine: PSI.
New Generation Comput. 1(2): 125-144 (1983) |