2006 | ||
---|---|---|
2 | EE | Dac Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel: Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. ASP-DAC 2006: 871-878 |
2002 | ||
1 | EE | James D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip Restle, Brian A. Zoric, Carl J. Anderson: The circuit and physical design of the POWER4 microprocessor. IBM Journal of Research and Development 46(1): 27-52 (2002) |
1 | Carl J. Anderson | [1] |
2 | Hans-Werner Anderson | [2] |
3 | Erwin Behnen | [2] |
4 | Mark Bolliger | [2] |
5 | Joachim G. Clabes | [1] |
6 | Sanjay Gupta | [2] |
7 | Paul E. Harvey | [2] |
8 | H. Peter Hofstee | [2] |
9 | Charles R. Johns | [2] |
10 | James A. Kahle | [2] |
11 | Atsushi Kameyama | [2] |
12 | Charles J. Kircher | [1] |
13 | Byron Krauter | [1] |
14 | Bob Le | [2] |
15 | Sang Lee | [2] |
16 | Tuyen V. Nguyen | [2] |
17 | John G. Petrovick | [1] [2] |
18 | Dac Pham | [2] |
19 | Mydung Pham | [2] |
20 | Juergen Pille | [2] |
21 | Stephen D. Posluszny | [2] |
22 | Phillip Restle (Phillip J. Restle) | [1] |
23 | Mack W. Riley | [2] |
24 | Joseph Verock | [2] |
25 | James D. Warnock | [1] [2] |
26 | Steve Weitzel | [2] |
27 | Dieter F. Wendel | [2] |
28 | Brian A. Zoric | [1] |