| 2007 |
|---|
| 7 | EE | Noriyuki Ito,
Hiroaki Komatsu,
Akira Kanuma,
Akihiro Yoshitake,
Yoshiyasu Tanamura,
Hiroyuki Sugiyama,
Ryoichi Yamashita,
Ken-ichi Nabeya,
Hironobu Yoshino,
Hitoshi Yamanaka,
Masahiro Yanagida,
Yoshitomo Ozeki,
Kinya Ishizaka,
Takeshi Kono,
Yutaka Isoda:
Design Methodology for 2.4GHz Dual-Core Microprocessor.
ASP-DAC 2007: 896-901 |
| 6 | EE | Wanping Zhang,
Ling Zhang,
Rui Shi,
He Peng,
Zhi Zhu,
Lew Chua-Eoan,
Rajeev Murgai,
Toshiyuki Shibuya,
Noriyuki Ito,
Chung-Kuan Cheng:
Fast power network analysis with multiple clock domains.
ICCD 2007: 456-463 |
| 2006 |
|---|
| 5 | EE | Noriyuki Ito,
Akira Kanuma,
Daisuke Maruyama,
Hitoshi Yamanaka,
Tsuyoshi Mochizuki,
Osamu Sugawara,
Chihiro Endoh,
Masahiro Yanagida,
Takeshi Kono,
Yutaka Isoda,
Kazunobu Adachi,
Takahisa Hiraide,
Shigeru Nagasawa,
Yaroku Sugiyama,
Eizo Ninoi:
Delay defect screening for a 2.16GHz SPARC64 microprocessor.
ASP-DAC 2006: 342-347 |
| 4 | EE | Noriyuki Ito,
Hideaki Katagiri,
Ryoichi Yamashita,
Hiroshi Ikeda,
Hiroyuki Sugiyama,
Hiroaki Komatsu,
Yoshiyasu Tanamura,
Akihiro Yoshitake,
Kazuhiro Nonomura,
Kinya Ishizaka,
Hiroaki Adachi,
Yutaka Mori,
Yutaka Isoda,
Yaroku Sugiyama:
Diagonal routing in high performance microprocessor design.
ASP-DAC 2006: 624-629 |
| 2004 |
|---|
| 3 | EE | Daisuke Maruyama,
Akira Kanuma,
Takashi Mochiyama,
Hiroaki Komatsu,
Yaroku Sugiyama,
Noriyuki Ito:
Detection of multiple transitions in delay fault test of SPARC64 microprocessor.
ICCAD 2004: 893-898 |
| 2003 |
|---|
| 2 | EE | Noriyuki Ito,
Hiroaki Komatsu,
Yoshiyasu Tanamura,
Ryoichi Yamashita,
Hiroyuki Sugiyama,
Yaroku Sugiyama,
Hirofumi Hamamura:
A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor.
ICCD 2003: 204-210 |
| 1990 |
|---|
| 1 | EE | Noriyuki Ito:
Automatic Incorporation of On-Chip Testability Circuits.
DAC 1990: 529-534 |
