| 2008 |
|---|
| 43 | EE | Pushkar Tripathi,
Rohan Jain,
Srikanth Kurra,
Preeti Ranjan Panda:
REWIRED - Register Write Inhibition by Resource Dedication.
ASP-DAC 2008: 28-31 |
| 42 | EE | B. V. N. Silpa,
Anjul Patney,
Tushar Krishna,
Preeti Ranjan Panda,
G. S. Visweswaran:
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors.
ICCAD 2008: 559-564 |
| 41 | EE | Preeti Ranjan Panda:
Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems.
International Journal of Parallel Programming 36(1): 1-2 (2008) |
| 2007 |
|---|
| 40 | EE | Srikanth Kurra,
Neeraj Kumar Singh,
Preeti Ranjan Panda:
The impact of loop unrolling on controller delay in high level synthesis.
DATE 2007: 391-396 |
| 39 | EE | Rahul Jain,
Preeti Ranjan Panda:
An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform.
ISCAS 2007: 1377-1380 |
| 38 | EE | Neeraj Goel,
Anshul Kumar,
Preeti Ranjan Panda:
Power Reduction in VLIW Processor with Compiler Driven Bypass Network.
VLSI Design 2007: 233-238 |
| 37 | EE | Rakesh Nalluri,
Rohan Garg,
Preeti Ranjan Panda:
Customization of Register File Banking Architecture for Low Power.
VLSI Design 2007: 239-244 |
| 36 | EE | Rahul Jain,
Preeti Ranjan Panda:
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform.
VLSI Design 2007: 813-818 |
| 35 | EE | Anup Gangwar,
M. Balakrishnan,
Preeti Ranjan Panda,
Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
International Journal of Parallel Programming 35(6): 507-527 (2007) |
| 2006 |
|---|
| 34 | EE | Preeti Ranjan Panda:
Abridged addressing: a low power memory addressing strategy.
ASP-DAC 2006: 892-897 |
| 33 | EE | Gagan Raj Gupta,
Madhur Gupta,
Preeti Ranjan Panda:
Rapid estimation of control delay from high-level specifications.
DAC 2006: 455-458 |
| 2005 |
|---|
| 32 | EE | Anup Gangwar,
M. Balakrishnan,
Preeti Ranjan Panda,
Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
DATE 2005: 730-735 |
| 31 | EE | Vikram Singh Saun,
Preeti Ranjan Panda:
Extracting Exact Finite State Machines from Behavioral SystemC Descriptions.
VLSI Design 2005: 280-285 |
| 2003 |
|---|
| 30 | EE | Ramesh Chandra,
Preeti Ranjan Panda,
Jörg Henkel,
Sri Parameswaran,
Loganath Ramachandran:
Specification and Design of Multi-Million Gate SOCs.
VLSI Design 2003: 18-19 |
| 29 | EE | Jaewon Seo,
Taewhan Kim,
Preeti Ranjan Panda:
Memory allocation and mapping in high-level synthesis - an integrated approach.
IEEE Trans. VLSI Syst. 11(5): 928-938 (2003) |
| 2002 |
|---|
| 28 | EE | Jaewon Seo,
Taewhan Kim,
Preeti Ranjan Panda:
An integrated algorithm for memory allocation and assignment in high-level synthesis.
DAC 2002: 608-611 |
| 27 | EE | Preeti Ranjan Panda,
Nikil D. Dutt:
Memory Architectures for Embedded Systems-On-Chip.
HiPC 2002: 647-662 |
| 26 | EE | Preeti Ranjan Panda,
Lakshmikantam Chitturi:
An energy-conscious algorithm for memory port allocation.
ICCAD 2002: 572-576 |
| 2001 |
|---|
| 25 | | Preeti Ranjan Panda,
Luc Séméria,
Giovanni De Micheli:
Cache-efficient memory layout of aggregate data structures.
ISSS 2001: 101-106 |
| 24 | | Preeti Ranjan Panda:
SystemC.
ISSS 2001: 75-80 |
| 23 | | Wolfgang Rosenstiel,
Brian Bailey,
Masahiro Fujita,
Guang R. Gao,
Rajesh K. Gupta,
Preeti Ranjan Panda:
New design paradigms.
ISSS 2001: 94 |
| 22 | | Doris Keitel-Schulz,
Norbert Wehn,
Francky Catthoor,
Preeti Ranjan Panda:
Embedded Memories in System Design: Technology, Application, Design and Tools.
VLSI Design 2001: 5-6 |
| 21 | EE | Preeti Ranjan Panda,
Francky Catthoor,
Nikil D. Dutt,
Koen Danckaert,
Erik Brockmeyer,
Chidamber Kulkarni,
Arnout Vandecappelle,
Per Gunnar Kjeldsberg:
Data and memory optimization techniques for embedded systems.
ACM Trans. Design Autom. Electr. Syst. 6(2): 149-206 (2001) |
| 20 | EE | Preeti Ranjan Panda,
Nikil D. Dutt,
Alexandru Nicolau,
Francky Catthoor,
Arnout Vandecappelle,
Erik Brockmeyer,
Chidamber Kulkarni,
Eddy de Greef:
Data Memory Organization and Optimizations in Application-Specific Systems.
IEEE Design & Test of Computers 18(3): 56-68 (2001) |
| 2000 |
|---|
| 19 | EE | Preeti Ranjan Panda,
Nikil D. Dutt,
Alexandru Nicolau:
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems.
ACM Trans. Design Autom. Electr. Syst. 5(3): 682-704 (2000) |
| 1999 |
|---|
| 18 | EE | Preeti Ranjan Panda:
Memory bank customization and assignment in behavioral synthesis.
ICCAD 1999: 477-481 |
| 17 | EE | Preeti Ranjan Panda,
Hiroshi Nakamura,
Nikil D. Dutt,
Alexandru Nicolau:
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance.
IEEE Trans. Computers 48(2): 142-149 (1999) |
| 16 | EE | Preeti Ranjan Panda,
Nikil D. Dutt:
Low-power memory mapping through reducing address bus activity.
IEEE Trans. VLSI Syst. 7(3): 309-320 (1999) |
| 15 | EE | Preeti Ranjan Panda,
Nikil D. Dutt,
Alexandru Nicolau:
Local memory exploration and optimization in embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(1): 3-13 (1999) |
| 1998 |
|---|
| 14 | EE | Preeti Ranjan Panda,
Nikil D. Dutt,
Alexandru Nicolau:
Data Cache Sizing for Embedded Processor Applications.
DATE 1998: 925-926 |
| 13 | EE | Preeti Ranjan Panda,
Nikil D. Dutt,
Alexandru Nicolau:
Incorporating DRAM access modes into high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 96-109 (1998) |
| 1997 |
|---|
| 12 | EE | Preeti Ranjan Panda,
Nikil D. Dutt,
Alexandru Nicolau:
Efficient utilization of scratch-pad memory in embedded processor applications.
ED&TC 1997: 7-11 |
| 11 | EE | Preeti Ranjan Panda,
Nikil D. Dutt,
Alexandru Nicolau:
Exploiting off-chip memory access modes in high-level synthesis.
ICCAD 1997: 333-340 |
| 10 | | Preeti Ranjan Panda,
Hiroshi Nakamura,
Nikil D. Dutt,
Alexandru Nicolau:
A Data Alignment Technique for Improving Cache Performance.
ICCD 1997: 587-592 |
| 9 | | Preeti Ranjan Panda,
Hiroshi Nakamura,
Nikil D. Dutt,
Alexandru Nicolau:
Improving cache Performance Through Tiling and Data Alignment.
IRREGULAR 1997: 167-185 |
| 8 | EE | Preeti Ranjan Panda,
Nikil D. Dutt,
Alexandru Nicolau:
Architectural Exploration and Optimization of Local Memory in Embedded Systems.
ISSS 1997: 90- |
| 7 | EE | Preeti Ranjan Panda,
Nikil D. Dutt:
Behavioral Array Mapping into Multiport Memories Targeting Low Power.
VLSI Design 1997: 268-273 |
| 6 | EE | Preeti Ranjan Panda,
Nikil D. Dutt,
Alexandru Nicolau:
Memory data organization for improved cache performance in embedded processor applications.
ACM Trans. Design Autom. Electr. Syst. 2(4): 384-409 (1997) |
| 1996 |
|---|
| 5 | EE | Preeti Ranjan Panda,
Nikil D. Dutt:
Low-power mapping of behavioral arrays to multiple memories.
ISLPED 1996: 289-292 |
| 4 | EE | Preeti Ranjan Panda,
Nikil D. Dutt,
Alexandru Nicolau:
Memory Organization for Improved Data Cache Performance in Embedded Processors.
ISSS 1996: 90-95 |
| 1995 |
|---|
| 3 | EE | Preeti Ranjan Panda,
Nikil D. Dutt:
1995 high level synthesis design repository.
ISSS 1995: 170-174 |
| 1993 |
|---|
| 2 | EE | Biswadip Mitra,
Preeti Ranjan Panda,
Parimal Pal Chaudhuri:
Estimating the Complexity of Synthesized Designs from FSM Specifications.
IEEE Design & Test of Computers 10(1): 30-35 (1993) |
| 1991 |
|---|
| 1 | | Biswadip Mitra,
Preeti Ranjan Panda,
Parimal Pal Chaudhuri:
A Flexible Scheme for State Assignment Based on Characteristics of the FSM.
ICCAD 1991: 226-229 |
