2006 |
6 | EE | Rajat Chaudhry,
Daniel L. Stasiak,
Stephen D. Posluszny,
Sang H. Dhong:
A cycle accurate power estimation tool.
ASP-DAC 2006: 867-870 |
5 | EE | Dac Pham,
Hans-Werner Anderson,
Erwin Behnen,
Mark Bolliger,
Sanjay Gupta,
H. Peter Hofstee,
Paul E. Harvey,
Charles R. Johns,
James A. Kahle,
Atsushi Kameyama,
John M. Keaty,
Bob Le,
Sang Lee,
Tuyen V. Nguyen,
John G. Petrovick,
Mydung Pham,
Juergen Pille,
Stephen D. Posluszny,
Mack W. Riley,
Joseph Verock,
James D. Warnock,
Steve Weitzel,
Dieter F. Wendel:
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.
ASP-DAC 2006: 871-878 |
2005 |
4 | EE | Sani R. Nassif,
Paul S. Zuchowski,
Claude Moughanni,
Mohamed Moosa,
Stephen D. Posluszny,
Ward Vercruysse:
The Titanic: what went wrong!
DAC 2005: 349-350 |
3 | EE | Daniel L. Stasiak,
Rajat Chaudhry,
Dennis Cox,
Stephen D. Posluszny,
James D. Warnock,
Steve Weitzel,
Dieter F. Wendel,
Michael Wang:
Cell Processor Low-Power Design Methodology.
IEEE Micro 25(6): 71-78 (2005) |
2000 |
2 | EE | Stephen D. Posluszny,
N. Aoki,
David Boerstler,
P. Coulman,
Sang H. Dhong,
Brian K. Flachs,
H. Peter Hofstee,
N. Kojima,
Ohsang Kwon,
K. Lee,
D. Meltzer,
Kevin J. Nowka,
J. Park,
J. Peter,
Joel Silberman,
Osamu Takahashi,
Paul Villarrubia:
"Timing closure by design, " a high frequency microprocessor design methodology.
DAC 2000: 712-717 |
1986 |
1 | EE | Stephen D. Posluszny:
SLS: An Advanced Symbolic Layout System for Bipolar and FET Design.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 450-458 (1986) |