| 2008 |
|---|
| 9 | EE | Navin Srivastava,
Roberto Suaya,
Kaustav Banerjee:
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate.
DATE 2008: 426-431 |
| 2007 |
|---|
| 8 | EE | Shashidhar Mysore,
Banit Agrawal,
Navin Srivastava,
Sheng-Chih Lin,
Kaustav Banerjee,
Timothy Sherwood:
3D Integration for Introspection.
IEEE Micro 27(1): 77-83 (2007) |
| 2006 |
|---|
| 7 | EE | Kaustav Banerjee,
Sheng-Chih Lin,
Navin Srivastava:
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems.
ASP-DAC 2006: 223-230 |
| 6 | EE | Shashidhar Mysore,
Banit Agrawal,
Navin Srivastava,
Sheng-Chih Lin,
Kaustav Banerjee,
Timothy Sherwood:
Introspective 3D chips.
ASPLOS 2006: 264-273 |
| 5 | EE | Kaustav Banerjee,
Navin Srivastava:
Are carbon nanotubes the future of VLSI interconnections?
DAC 2006: 809-814 |
| 4 | EE | Gian Luca Loi,
Banit Agrawal,
Navin Srivastava,
Sheng-Chih Lin,
Timothy Sherwood,
Kaustav Banerjee:
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy.
DAC 2006: 991-996 |
| 2005 |
|---|
| 3 | | Navin Srivastava,
Kaustav Banerjee:
Performance analysis of carbon nanotube interconnects for VLSI applications.
ICCAD 2005: 383-390 |
| 2 | EE | Sheng-Chih Lin,
Navin Srivastava,
Kaustav Banerjee:
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs.
ICCD 2005: 411-416 |
| 1 | EE | Navin Srivastava,
Xiaoning Qi,
Kaustav Banerjee:
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits.
ISQED 2005: 346-351 |
