Sri Parameswaran

2009
57	EE	Yee Jern Chong, Sri Parameswaran: Flexible multi-mode embedded floating-point unit for field programmable gate arrays. FPGA 2009: 171-180
56	EE	Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Roshan G. Ragel: Security and Dependability of Embedded Systems: A Computer Architects' Perspective. VLSI Design 2009: 30-32
55	EE	Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran: Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
2008
54	EE	Jeremy Chan, Sri Parameswaran: NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks. ASP-DAC 2008: 265-270
53	EE	Haris Javaid, Sri Parameswaran: Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. CODES+ISSS 2008: 1-6
52	EE	Krutartha Patel, Sri Parameswaran: LOCS: a low overhead profiler-driven design flow for security of MPSoCs. CODES+ISSS 2008: 79-84
51	EE	Yee Jern Chong, Sri Parameswaran: Rapid application specific floating-point unit generation with bit-alignment. DAC 2008: 62-67
50	EE	Krutartha Patel, Sri Parameswaran: SHIELD: a software hardware design methodology for security and reliability of MPSoCs. DAC 2008: 858-861
49	EE	Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran: A Formal Approach To The Protocol Converter Problem. DATE 2008: 294-299
48	EE	Jude Angelo Ambrose, Sri Parameswaran, Aleksandar Ignjatovic: MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. ICCAD 2008: 678-684
47	EE	Jorgen Peddersen, Sri Parameswaran: Low-Impact Processor for Dynamic Runtime Power Management. IEEE Design & Test of Computers 25(1): 52-62 (2008)
46	EE	Seng Lin Shee, Andrea Erdos, Sri Parameswaran: Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG. International Journal of Parallel Programming 36(1): 140-162 (2008)
45	EE	Jorgen Peddersen, Sri Parameswaran: Energy Driven Application Self-Adaptation at Run-time. JCP 3(3): 14-24 (2008)
2007
44	EE	Jorgen Peddersen, Sri Parameswaran: CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. ASP-DAC 2007: 890-895
43	EE	Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran: A smart random code injection to mask power analysis based side channel attacks. CODES+ISSS 2007: 51-56
42	EE	Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran: RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks. DAC 2007: 489-492
41	EE	Seng Lin Shee, Sri Parameswaran: Design Methodology for Pipelined Heterogeneous Multiprocessor System. DAC 2007: 811-816
40	EE	Yee Jern Chong, Sri Parameswaran: Automatic application specific floating-point unit generation. DATE 2007: 461-466
39	EE	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel: Instruction trace compression for rapid instruction cache simulation. DATE 2007: 803-808
38	EE	Jorgen Peddersen, Sri Parameswaran: Energy Driven Application SelfAdaptation. VLSI Design 2007: 385-390
2006
37	EE	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran: A novel instruction scratchpad memory optimization method based on concomitance metric. ASP-DAC 2006: 612-617
36	EE	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran: Finding optimal L1 cache configuration for embedded systems. ASP-DAC 2006: 796-801
35	EE	Roshan G. Ragel, Sri Parameswaran: Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability. CODES+ISSS 2006: 100-105
34	EE	Seng Lin Shee, Andrea Erdos, Sri Parameswaran: Heterogeneous multiprocessor implementations for JPEG: : a case study. CODES+ISSS 2006: 217-222
33	EE	Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic: Application specific forwarding network and instruction encoding for multi-pipe ASIPs. CODES+ISSS 2006: 241-246
32	EE	Roshan G. Ragel, Sri Parameswaran: IMPRES: integrated monitoring for processor reliability and security. DAC 2006: 502-505
31	EE	Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran: Customization of application specific heterogeneous multi-pipeline processors. DATE 2006: 746-751
30	EE	Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran: ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. VLSI Design 2006: 575-580
29	EE	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran: Exploiting statistical information for implementation of instruction scratchpad memory in embedded system. IEEE Trans. VLSI Syst. 14(8): 816-829 (2006)
2005
28	EE	Newton Cheung, Sri Parameswaran, Jörg Henkel: Battery-aware instruction generation for embedded processors. ASP-DAC 2005: 553-556
27	EE	Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia: Micro embedded monitoring for security in application specific instruction-set processors. CASES 2005: 304-314
26	EE	Seng Lin Shee, Sri Parameswaran, Newton Cheung: Novel architecture for loop acceleration: a case study. CODES+ISSS 2005: 297-302
25		Jeremy Chan, Sri Parameswaran: NoCEE: energy macro-model extraction methodology for network on chip routers. ICCAD 2005: 254-259
24	EE	Hui Guo, Sri Parameswaran: Balancing System Level Pipelines with Stage Voltage Scaling. ISVLSI 2005: 287-289
23	EE	Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran: Rapid Embedded Hardware/Software System Generation. VLSI Design 2005: 111-116
22	EE	Sri Parameswaran, Jörg Henkel: Instruction code mapping for performance increase and energy reduction in embedded computer systems. IEEE Trans. VLSI Syst. 13(4): 498-502 (2005)
2004
21	EE	Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran: Dual-pipeline heterogeneous ASIP design. CODES+ISSS 2004: 12-17
20	EE	Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan: MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. DATE 2004: 1020-1027
19	EE	Newton Cheung, Sri Parameswaran, Jörg Henkel: A quantitative study and estimation models for extensible instructions in embedded processors. ICCAD 2004: 183-189
18	EE	Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic: Hardware/software managed scratchpad memory for embedded system. ICCAD 2004: 370-377
17	EE	Jeremy Chan, Sri Parameswaran: NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. VLSI Design 2004: 717-720
2003
16	EE	Newton Cheung, Jörg Henkel, Sri Parameswaran: Rapid Configuration and Instruction Selection for an ASIP: A Case Study. DATE 2003: 10802-10809
15	EE	Newton Cheung, Sri Parameswaran, Jörg Henkel: INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors. ICCAD 2003: 291-298
14	EE	Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran: Specification and Design of Multi-Million Gate SOCs. VLSI Design 2003: 18-19
2002
13		Jörg Henkel, Xiaobo Sharon Hu, Rajesh Gupta, Sri Parameswaran: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002 ACM 2002
12	EE	Tony Han, Sri Parameswaran: SWASAD: An ASIC Design for High Speed DNA Sequence Matching. VLSI Design 2002: 541-546
2001
11	EE	Sri Parameswaran: Code placement in hardware/software co-synthesis to improve performance and reduce cost. DATE 2001: 626-632
10	EE	Sri Parameswaran, Jörg Henkel: I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency. ICCAD 2001: 635-
2000
9	EE	Allan Rae, Sri Parameswaran: Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation. ASP-DAC 2000: 147-152
8	EE	V. E. Boros, Aleksandar D. Rakic, Sri Parameswaran: High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system. DAC 2000: 221-226
1998
7		Sri Parameswaran: HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial). ASP-DAC 1998: 19-22
6		Sri Parameswaran, Hui Guo: Power Reduction in Pipelines. ASP-DAC 1998: 545-550
5		Hui Guo, Sri Parameswaran: Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. ASP-DAC 1998: 99-104
4	EE	Allan Rae, Sri Parameswaran: Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution. ISSS 1998: 83-88
1995
3	EE	Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran: Reclocking for high-level synthesis. ASP-DAC 1995
2	EE	Matthew F. Parkinson, Sri Parameswaran: Profiling in the ASP codesign environment. ISSS 1995: 128-133
1994
1	EE	Sayed Mohammad Kia, Sri Parameswaran: Design automation of self checking circuits. EURO-DAC 1994: 252-257

Coauthor Index

1	Jude Angelo Ambrose	[42] [43] [48]
2	Karin Avnit	[49] [55]
3	V. E. Boros	[8]
4	Jeremy Chan	[17] [20] [25] [54]
5	Ramesh Chandra	[14]
6	Newton Cheung	[15] [16] [19] [20] [26] [28]
7	Yee Jern Chong	[40] [51] [57]
8	Vijay D'Silva	[49] [55]
9	Nikil D. Dutt (Nikil Dutt)	[3]
10	Andrea Erdos	[34] [46]
11	Hui Guo	[5] [6] [21] [24] [31] [33]
12	Rajesh K. Gupta (Rajesh Gupta)	[13]
13	Tony Han	[12]
14	Jörg Henkel	[10] [13] [14] [15] [16] [19] [20] [22] [28] [39] [56]
15	Xiaobo Sharon Hu (Xiaobo Hu)	[13]
16	Aleksandar Ignjatovic	[18] [29] [33] [36] [37] [39] [48]
17	Andhi Janapsatya	[18] [23] [29] [36] [37] [39]
18	Haris Javaid	[53]
19	Pradip K. Jha	[3]
20	Sayed Mohammad Kia	[1] [27]
21	Ivan Siu-Chuang Lu	[30]
22	Preeti Ranjan Panda	[14]
23	Matthew F. Parkinson	[2]
24	Krutartha Patel	[50] [52]
25	Jorgen Peddersen	[23] [38] [44] [45] [47]
26	Swarnalatha Radhakrishnan	[21] [31] [33]
27	Allan Rae	[4] [9]
28	Roshan G. Ragel	[27] [32] [35] [42] [43] [56]
29	Aleksandar D. Rakic	[8]
30	Loganath Ramachandran	[14]
31	S. Ramesh (Sethu Ramesh)	[49] [55]
32	Seng Lin Shee	[23] [26] [34] [41] [46]
33	Arcot Sowmya	[49] [55]
34	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[56]
35	Neil Weste	[30]

Colors in the list of coauthors