| 2008 |
|---|
| 9 | EE | Meng-Chiou Wu,
Rung-Bin Lin,
Shih-Cheng Tsai:
Chip placement in a reticle for multiple-project wafer fabrication.
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 8 | EE | Meng-Chiou Wu,
Rung-Bin Lin:
Finding Dicing Plans for Multiple Project wafers fabricated with Shuttle Mask.
Journal of Circuits, Systems, and Computers 17(1): 15-31 (2008) |
| 2007 |
|---|
| 7 | | Rung-Bin Lin,
Da-Wei Hsu,
Ming-Hsine Kuo,
Meng-Chiou Wu:
Reticle Exposure Plans for Multi-Project Wafers.
DDECS 2007: 341-344 |
| 2006 |
|---|
| 6 | EE | Rung-Bin Lin,
Meng-Chiou Wu,
Wei-Chiu Tseng,
Ming-Hsine Kuo,
Tsai-Ying Lin,
Shr-Cheng Tsai:
Design space exploration for minimizing multi-project wafer production cost.
ASP-DAC 2006: 783-788 |
| 2005 |
|---|
| 5 | EE | Meng-Chiou Wu,
Rung-Bin Lin:
Reticle floorplanning of flexible chips for multi-project wafers.
ACM Great Lakes Symposium on VLSI 2005: 494-497 |
| 4 | EE | Meng-Chiou Wu,
Rung-Bin Lin:
Multiple project wafers for medium-volume IC production.
ISCAS (5) 2005: 4725-4728 |
| 3 | EE | Meng-Chiou Wu,
Rung-Bin Lin:
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers.
ISQED 2005: 610-615 |
| 2 | EE | Meng-Chiou Wu,
Rung-Bin Lin:
A Comparative Study on Dicing of Multiple Project Wafers.
ISVLSI 2005: 314-315 |
| 1998 |
|---|
| 1 | EE | Rung-Bin Lin,
Meng-Chiou Wu:
A New Statistical Approach to Timing Analysis of VLSI Circuits.
VLSI Design 1998: 507- |
