Yuzo Takamatsu

2009
49	EE	Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume: A Novel Approach for Improving the Quality of Open Fault Diagnosis. VLSI Design 2009: 85-90
48	EE	Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu: Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. VLSI Design 2009: 91-96
2008
47	EE	Koji Yamazaki, Yuzo Takamatsu: A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information. IEICE Transactions 91-D(3): 661-666 (2008)
46	EE	Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki: Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information. IEICE Transactions 91-D(3): 675-682 (2008)
45	EE	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. IEICE Transactions 91-D(3): 690-699 (2008)
44	EE	Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Post-BIST Fault Diagnosis for Multiple Faults. IEICE Transactions 91-D(3): 771-775 (2008)
2007
43	EE	Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu: Timing-Aware Diagnosis for Small Delay Defects. DFT 2007: 223-234
42	EE	Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume: Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. DFT 2007: 243-251
41	EE	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu: Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. VLSI Design 2007: 781-786
2006
40	EE	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. ASP-DAC 2006: 659-664
39	EE	Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT 2006: 401-109
38	EE	Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu: On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Transactions 89-D(11): 2748-2755 (2006)
2005
37	EE	T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu: On the fault diagnosis in the presence of unknown fault models using pass/fail information. ISCAS (3) 2005: 2987-2990
36	EE	Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu: A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 252-263 (2005)
35	EE	Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu: Test cost reduction for logic circuits: Reduction of test data volume and test application time. Systems and Computers in Japan 36(6): 69-83 (2005)
2004
34	EE	Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu: Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. Asian Test Symposium 2004: 216-221
33	EE	Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu: Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. Asian Test Symposium 2004: 222-227
32	EE	Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu: Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. Asian Test Symposium 2004: 46-49
2003
31	EE	Hiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu: BIST Based Fault Diagnosis Using Ambiguous Test Set. DFT 2003: 89-96
30	EE	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz: A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ICCD 2003: 397-
2002
29	EE	Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu: Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. Asian Test Symposium 2002: 242-247
28	EE	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu: A Method to Reduce Power Dissipation during Test for Sequential Circuits. Asian Test Symposium 2002: 326-331
27	EE	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu: Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. DELTA 2002: 431-433
26	EE	Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu: An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. PRDC 2002: 275-282
25	EE	Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu: On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 362-368 (2002)
2001
24	EE	Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu: Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. Asian Test Symposium 2001: 63-
23	EE	Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu: Test Generation for Double Stuck-at Faults. Asian Test Symposium 2001: 71-75
22		Keith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu: On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits. ITC 2001: 568-577
2000
21	EE	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Fault models and test generation for IDDQ testing: embedded tutorial. ASP-DAC 2000: 509-514
20	EE	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita: Test sequence compaction for sequential circuits with reset states. Asian Test Symposium 2000: 165-170
19	EE	Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu: General BIST-Amenable Method of Test Generation for Iterative Logic Arrays. VTS 2000: 171-178
18	EE	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electronic Testing 16(5): 443-451 (2000)
17	EE	Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita: Static test compaction for IDDQ testing of bridging faults in sequential circuits. Systems and Computers in Japan 31(11): 41-50 (2000)
16	EE	Tetsuro Minamiyama, Yuzo Takamatsu: Identification of redundant faults in combinational circuits. Systems and Computers in Japan 31(6): 65-73 (2000)
1999
15	EE	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 141-146
14	EE	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Nobuhiro Yanagida: Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators. Asian Test Symposium 1999: 341-346
13	EE	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu: A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations. VTS 1999: 64-69
1998
12	EE	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu: Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation. Asian Test Symposium 1998: 108-112
11	EE	Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu: Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths. Asian Test Symposium 1998: 237-
1997
10	EE	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga: A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. Asian Test Symposium 1997: 320-325
9	EE	Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu: Design of C-Testable Multipliers Based on the Modified Booth Algorithm. Asian Test Symposium 1997: 42-47
8	EE	Hiroshi Takahashi, Takashi Watanabe, Toshiyuki Matsunaga, Yuzo Takamatsu: Tests for small gate delay faults in combinational circuits and a test generation method. Systems and Computers in Japan 28(6): 68-76 (1997)
1996
7		Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu: Multiple Fault Diagnosis in Sequential Circuits Using Sensitizing Sequence Pairs. FTCS 1996: 86-95
1995
6	EE	Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu: Generation of tenacious tests for small gate delay faults in combinational circuits. Asian Test Symposium 1995: 332-338
5	EE	Hiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu: Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing. Asian Test Symposium 1995: 58-64
4	EE	Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu: Multiple Fault Diagnosis by Sensitizing Input Pairs. IEEE Design & Test of Computers 12(3): 44-52 (1995)
1990
3		Masakatu Morii, Yuzo Takamatsu: Exponetiation in Finite Fields Using Dual Basis Multiplier. AAECC 1990: 354-366
2	EE	Yuzo Takamatsu, Kozo Kinoshita: Extended selection of switching target faults in CONT algorithm for test generation. J. Electronic Testing 1(3): 183-189 (1990)
1989
1	EE	Yuzo Takamatsu, Kozo Kinoshita: CONT: a concurrent test generation system. IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 966-972 (1989)

Coauthor Index

1	Takashi Aikyo	[39] [42] [43] [44] [46] [48] [49]
2	Hidekazu Ayano	[31]
3	Kwame Osei Boateng	[9] [10] [12] [13] [14] [19] [25]
4	Masaki Hashizume	[42] [48] [49]
5	Yoshinobu Higami	[15] [17] [18] [20] [21] [23] [24] [27] [28] [30] [32] [33] [34] [35] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [48] [49]
6	Hideyuki Ichihara	[35]
7	Shuhei Kadoyama	[39] [44]
8	Seiji Kajihara	[30] [32] [35] [38]
9	Keith J. Keller	[22] [29] [36]
10	Toru Kikkawa	[42]
11	Kozo Kinoshita	[1] [2] [15] [17] [18] [20] [21]
12	Shin-ya Kobayashi	[27] [28] [30] [32] [38] [40] [45]
13	Kim T. Le	[29] [36]
14	Toshiyuki Matsunaga	[8] [10]
15	Tetsuro Minamiyama	[16]
16	Masakatu Morii	[3]
17	Kyohei Ono	[43]
18	Junichi Ootsu	[43]
19	Marong Phadoongsidhi	[24]
20	Irith Pomeranz	[30] [38]
21	Kewal K. Saluja	[15] [17] [18] [21] [22] [24] [25] [26] [29] [36] [40] [41] [45]
22	Yasuo Sato	[39] [44]
23	Yuichi Sato	[33]
24	T. Seiyama	[37]
25	Hiroshi Takahashi	[4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [19] [22] [24] [25] [26] [29] [31] [33] [34] [36] [37] [39] [40] [41] [42] [43] [44] [45] [46] [48] [49]
26	Naoko Takahashi	[23]
27	Yasunori Tsugaoka	[31]
28	Toshiyuki Tsutsumi	[48] [49]
29	Takashi Watanabe	[6] [8]
30	Yukihiro Yamamoto	[34]
31	Kazuo Yamazaki	[37]
32	Koji Yamazaki	[39] [44] [46] [47] [48] [49]
33	Nobuhiro Yanagida	[4] [5] [7] [11] [14]
34	Hiroyuki Yotsuyanagi	[42] [48] [49]

Colors in the list of coauthors