| 2009 |
|---|
| 14 | EE | Yu-Ru Hong,
Juinn-Dar Huang:
Reducing fault dictionary size for million-gate large circuits.
ACM Trans. Design Autom. Electr. Syst. 14(2): (2009) |
| 2008 |
|---|
| 13 | EE | Wei-Sheng Huang,
Yu-Ru Hong,
Juinn-Dar Huang,
Ya-Shih Huang:
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing.
ASP-DAC 2008: 16-21 |
| 2007 |
|---|
| 12 | EE | Bu-Ching Lin,
Geeng-Wei Lee,
Juinn-Dar Huang,
Jing-Yang Jou:
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses.
ASP-DAC 2007: 165-170 |
| 11 | EE | Yu-Ru Hong,
Juinn-Dar Huang:
Fault Dictionary Size Reduction for Million-Gate Large Circuits.
ASP-DAC 2007: 829-834 |
| 2006 |
|---|
| 10 | EE | Man-Yun Su,
Che-Hua Shih,
Juinn-Dar Huang,
Jing-Yang Jou:
FSM-based transaction-level functional coverage for interface compliance verification.
ASP-DAC 2006: 448-453 |
| 9 | EE | Chien-Hua Chen,
Geeng-Wei Lee,
Juinn-Dar Huang,
Jing-Yang Jou:
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication.
ASP-DAC 2006: 600-605 |
| 2004 |
|---|
| 8 | EE | Geeng-Wei Lee,
Juinn-Dar Huang,
Jing-Yang Jou,
Chun-Yao Wang:
Verification on Port Connections.
ITC 2004: 830-836 |
| 2001 |
|---|
| 7 | EE | Jie-Hong Roland Jiang,
Jing-Yang Jou,
Juinn-Dar Huang:
Unified functional decomposition via encoding for FPGA technology mapping.
IEEE Trans. VLSI Syst. 9(2): 251-260 (2001) |
| 2000 |
|---|
| 6 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen:
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.
IEEE Trans. VLSI Syst. 8(4): 392-400 (2000) |
| 1998 |
|---|
| 5 | EE | Jie-Hong Roland Jiang,
Jing-Yang Jou,
Juinn-Dar Huang:
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis.
DAC 1998: 712-717 |
| 4 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen,
Hsien-Ho Chuang:
On circuit clustering for area/delay tradeoff under capacity and pin constraints.
IEEE Trans. VLSI Syst. 6(4): 634-642 (1998) |
| 1996 |
|---|
| 3 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen:
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.
ICCAD 1996: 13-17 |
| 1995 |
|---|
| 2 | EE | Wen-Zen Shen,
Juinn-Dar Huang,
Shih-Min Chao:
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping.
DAC 1995: 65-69 |
| 1 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen:
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.
ICCAD 1995: 359-363 |
