2008 |
24 | EE | Vítor Silva,
Rui Duarte,
Mário P. Véstias,
Horácio C. Neto:
Multiplier-based double precision floating point divider according to the IEEE-754 standard.
ARC 2008: 260-265 |
23 | EE | Rui Marcelino,
Horácio C. Neto,
João M. P. Cardoso:
Sorting Units for FPGA-Based Embedded Systems.
DIPES 2008: 11-22 |
22 | EE | Horácio C. Neto,
Mário P. Véstias:
Decimal multiplier on FPGA using embedded binary multipliers.
FPL 2008: 197-202 |
2007 |
21 | EE | Mário P. Véstias,
Horácio C. Neto:
Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems.
FPL 2007: 389-394 |
2006 |
20 | EE | Mário P. Véstias,
Horácio C. Neto:
Area/Performance Improvement of NoC Architectures.
ARC 2006: 193-198 |
19 | EE | Mário P. Véstias,
Horácio C. Neto:
Co-synthesis of a configurable SoC platform based on a network on chip architecture.
ASP-DAC 2006: 48-53 |
18 | EE | Mário P. Véstias,
Horácio C. Neto:
A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation.
FPL 2006: 1-4 |
17 | EE | Goncalo M. de Matos,
Horácio C. Neto:
On Reconfigurable Architectures for Efficient Matrix Inversion.
FPL 2006: 1-6 |
16 | EE | Mário P. Véstias,
Horácio C. Neto:
Area and performance optimization of a generic network-on-chip architecture.
SBCCI 2006: 68-73 |
2005 |
15 | | Pedro Domingos,
Fernando M. Silva,
Horácio C. Neto:
An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning.
FPL 2005: 89-94 |
14 | EE | Ricardo Ferreira,
João M. P. Cardoso,
Andre Toledo,
Horácio C. Neto:
Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping.
SAMOS 2005: 41-50 |
2004 |
13 | EE | Ricardo Ferreira,
João M. P. Cardoso,
Horácio C. Neto:
An Environment for Exploring Data-Driven Architectures.
FPL 2004: 1022-1026 |
2003 |
12 | EE | Mário P. Véstias,
Horácio C. Neto:
DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures.
SBCCI 2003: 85- |
11 | EE | João M. P. Cardoso,
Horácio C. Neto:
Compilation for FPGA-Based Reconfigurable Hardware.
IEEE Design & Test of Computers 20(2): 65-75 (2003) |
2002 |
10 | EE | Mário P. Véstias,
Horácio C. Neto:
System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures.
IEEE International Workshop on Rapid System Prototyping 2002: 130-137 |
2001 |
9 | EE | João M. P. Cardoso,
Horácio C. Neto:
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines.
FPL 2001: 523-533 |
8 | EE | Paulo F. Flores,
Horácio C. Neto,
João P. Marques Silva:
An exact solution to the minimum size test pattern problem.
ACM Trans. Design Autom. Electr. Syst. 6(4): 629-644 (2001) |
1999 |
7 | EE | João M. P. Cardoso,
Horácio C. Neto:
Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System.
FCCM 1999: 2-11 |
6 | EE | Paulo F. Flores,
Horácio C. Neto,
João P. Marques Silva:
On Applying Set Covering Models to Test Set Compaction.
Great Lakes Symposium on VLSI 1999: 8-11 |
5 | EE | Paulo F. Flores,
Horácio C. Neto,
K. Chakrabarty,
João P. Marques Silva:
Test pattern generation for width compression in BIST.
ISCAS (1) 1999: 114-118 |
4 | | João M. P. Cardoso,
Horácio C. Neto:
An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs.
VLSI 1999: 485-496 |
3 | EE | Paulo F. Flores,
José C. Costa,
Horácio C. Neto,
José C. Monteiro,
João P. Marques Silva:
Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation.
VLSI Design 1999: 37-41 |
1994 |
2 | | José C. Monteiro,
James H. Kukula,
Srinivas Devadas,
Horácio C. Neto:
Bitwise Encoding of Finite State Machines.
VLSI Design 1994: 379-382 |
1992 |
1 | EE | Luis Miguel Silveira,
Jacob K. White,
Horácio C. Neto,
Luís M. Vidigal:
On exponential fitting for circuit simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 566-574 (1992) |