2008 |
27 | EE | Yuichi Tanji,
Takayuki Watanabe,
Hideki Asai:
Generating stable and sparse reluctance/inductance matrix under insufficient conditions.
ASP-DAC 2008: 164-169 |
26 | EE | Yuya Nakazono,
Hideki Asai:
Acceleration of ADI-FDTD Method by Gauss-Seidel Relaxation Approach.
IEICE Transactions 91-A(2): 550-553 (2008) |
25 | EE | Tadatoshi Sekine,
Yuichi Tanji,
Hideki Asai:
Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane.
IEICE Transactions 91-A(9): 2450-2455 (2008) |
2007 |
24 | EE | Yuya Nakazono,
Hideki Asai:
Application of Relaxation-Based Technique to ADI-FDTD Method and Its Estimation.
ISCAS 2007: 1489-1492 |
23 | EE | Takayuki Watanabe,
Yuichi Tanji,
Hidemasa Kubota,
Hideki Asai:
Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm.
IEICE Transactions 90-A(2): 388-397 (2007) |
2006 |
22 | EE | Takayuki Watanabe,
Yuichi Tanji,
Hidemasa Kubota,
Hideki Asai:
Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters.
ASP-DAC 2006: 832-837 |
21 | EE | Yuichi Tanji,
Takayuki Watanabe,
Hidemasa Kubota,
Hideki Asai:
Large scale RLC circuit analysis using RLCG-MNA formulation.
DATE 2006: 45-46 |
20 | EE | Yuichi Tanji,
Hideki Asai,
Masayoshi Oda,
Yoshifumi Nishio,
Akio Ushida:
Fast timing analysis of plane circuits via two-layer CNN-based modeling.
ISCAS 2006 |
19 | EE | Yuichi Tanji,
Takayuki Watanabe,
Hidemasa Kubota,
Hideki Asai:
Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation.
ISQED 2006: 393-400 |
18 | EE | Hidemasa Kubota,
Yuichi Tanji,
Takayuki Watanabe,
Hideki Asai:
An Enhanced Time-Domain Circuit Simulation Technique Based on LIM.
IEICE Transactions 89-A(5): 1505-1506 (2006) |
2005 |
17 | EE | Hirokazu Yamagishi,
Hiroshi Ninomiya,
Hideki Asai:
Three dimensional module packing by simulated annealing.
Congress on Evolutionary Computation 2005: 1069-1074 |
16 | EE | Takashi Mine,
Hidemasa Kubota,
Atsushi Kamo,
Takayuki Watanabe,
Hideki Asai:
Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits.
ISCAS (5) 2005: 4903-4906 |
15 | EE | Takayuki Watanabe,
Hideki Asai:
Modeling of power distribution networks with signal lines for SPICE simulators.
ISCAS (6) 2005: 5774-5777 |
14 | EE | Yuichi Tanji,
Masaya Suzuki,
Takayuki Watanabe,
Hideki Asai:
New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data.
IEICE Transactions 88-A(2): 524-532 (2005) |
2004 |
13 | EE | Yuichi Tanji,
Hideki Asai:
Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects.
DAC 2004: 810-813 |
12 | EE | Takashi Mine,
Hidemasa Kubota,
Atsushi Kamo,
Takayuki Watanabe,
Hideki Asai:
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits.
DATE 2004: 1327-1333 |
2003 |
11 | EE | Takayuki Watanabe,
Hideki Asai:
Analysis of PCB interconnects using electromagnetic reduction technique.
ISCAS (3) 2003: 498-501 |
2001 |
10 | EE | Masaya Suzuki,
H. Miyashita,
Atsushi Kamo,
Takayuki Watanabe,
Hideki Asai:
High-speed interconnect simulation using MIMO type of adaptive least square method.
ISCAS (5) 2001: 327-330 |
9 | | Shinsuke Manabe,
Hideki Asai:
A Neuro-Based Optimization Algorithm for Tiling Problems with Rotation.
Neural Processing Letters 13(3): 267-275 (2001) |
2000 |
8 | EE | Masahiro Yoshida,
Hideki Asai,
Takeshi Kamio:
Neuro-Based Human-Face Recognition with 2-Dimensional Discrete Walsh Transform.
IJCNN (3) 2000: 315-319 |
7 | EE | Teru Yoneyama,
Hideki Asai,
Hiroshi Ninomiya:
Design Method of Limit Cycle Generator by Hysteresis Neural Networks.
IJCNN (3) 2000: 500-505 |
1995 |
6 | | Takeshi Kamio,
Hiroshi Ninomiya,
Hideki Asai:
Convergence of Hopfield Neural Network for Orthogonal Transformation.
ISCAS 1995: 493-496 |
5 | | Hiroshi Ninomiya,
Hideki Asai:
Orthogonalized Steepest Descent Method for Solving Nonlinear Equations.
ISCAS 1995: 740-743 |
1994 |
4 | | Masaki Ishida,
Koichi Hayashi,
Masakatsu Nishigaki,
Hideki Asai:
Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits.
ISCAS 1994: 411-414 |
3 | | Vijaya Gopal Bandi,
Hideki Asai:
Transient Simulation of Coupled Lossy Interconnects by Window Partitioning Technique.
ISCAS 1994: 419-422 |
2 | | Takeshi Senoo,
Hiroaki Makino,
Hideki Asai:
Relaxation-Based Steady-State Analysis of Single- and Multi-Conductor Transmission Lines in Frequency Domain.
ISCAS 1994: 5-8 |
1 | | Masakatsu Nishigaki,
Nobuyuki Tanaka,
Hideki Asai:
Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective Trace.
ISCAS 1994: 9-12 |