2008 |
17 | EE | Jin Guo,
Antonis Papanikolaou,
Michele Stucchi,
Kristof Croes,
Zsolt Tokei,
Francky Catthoor:
A tool flow for predicting system level timing failures due to interconnect reliability degradation.
ACM Great Lakes Symposium on VLSI 2008: 291-296 |
16 | EE | Concepción Sanz,
Manuel Prieto,
José Ignacio Gómez,
Antonis Papanikolaou,
Miguel Miranda,
Francky Catthoor:
Combining system scenarios and configurable memories to tolerate unpredictability.
ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
2007 |
15 | EE | Jin Guo,
Antonis Papanikolaou,
Francky Catthoor:
Topology exploration for energy efficient intra-tile communication.
ASP-DAC 2007: 178-183 |
14 | EE | Antonis Papanikolaou,
Hua Wang,
Miguel Miranda,
Francky Catthoor:
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
IOLTS 2007: 121 |
13 | EE | Jin Guo,
Antonis Papanikolaou,
H. Zhang,
Francky Catthoor:
Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture.
IEEE Trans. VLSI Syst. 15(8): 941-944 (2007) |
2006 |
12 | EE | Kris Heyrman,
Antonis Papanikolaou,
Francky Catthoor,
Peter Veelaert,
Koen De Bosschere,
Wilfried Philips:
Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture.
ARC 2006: 52-58 |
11 | EE | Jin Guo,
Antonis Papanikolaou,
Pol Marchal,
Francky Catthoor:
Physical design implementation of segmented buses to reduce communication energy.
ASP-DAC 2006: 42-47 |
10 | EE | Antonis Papanikolaou,
T. Grabner,
Miguel Miranda,
P. Roussel,
Francky Catthoor:
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations.
CODES+ISSS 2006: 253-258 |
9 | EE | Concepción Sanz,
Manuel Prieto,
Antonis Papanikolaou,
Miguel Miranda,
Francky Catthoor:
System-level process variability compensation on memory organizations of dynamic applications: a case study.
ISQED 2006: 376-382 |
8 | EE | Jin Guo,
Antonis Papanikolaou,
Pol Marchal,
Francky Catthoor:
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture.
SLIP 2006: 75-81 |
7 | EE | Antonis Papanikolaou,
Miguel Miranda,
Hua Wang,
Francky Catthoor,
M. Satyakiran,
Pol Marchal,
Ben Kaczer,
C. Bruynseraede,
Zsolt Tokei:
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
VLSI-SoC 2006: 342-347 |
2005 |
6 | EE | Antonis Papanikolaou,
F. Lobmaier,
Hua Wang,
Miguel Miranda,
Francky Catthoor:
A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications.
CODES+ISSS 2005: 117-122 |
5 | EE | Hua Wang,
Miguel Miranda,
Antonis Papanikolaou,
Francky Catthoor,
Wim Dehaene:
Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.
IEEE Trans. VLSI Syst. 13(10): 1127-1135 (2005) |
2004 |
4 | EE | Hua Wang,
Antonis Papanikolaou,
Miguel Miranda,
Francky Catthoor:
A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement.
ASP-DAC 2004: 759-761 |
3 | EE | Antonis Papanikolaou,
Miguel Miranda,
Francky Catthoor:
Overcoming the "Memory Wall" by improved system design exploration and a link to process technology options.
Conf. Computing Frontiers 2004: 202-211 |
2003 |
2 | EE | Antonis Papanikolaou,
Miguel Miranda,
Francky Catthoor,
Henk Corporaal,
Hugo De Man,
David De Roest,
Michele Stucchi,
Karen Maex:
Global interconnect trade-off for technology over memory modules to application level: case study.
SLIP 2003: 125-132 |
2002 |
1 | EE | Antonis Papanikolaou,
Miguel Miranda,
Francky Catthoor,
Henk Corporaal,
Hugo De Man,
David De Roest,
Michele Stucchi,
Karen Maex:
Interconnect exploration for future wire dominated technologies.
SLIP 2002: 105-106 |