2006 |
9 | EE | Shunitsu Kohara,
Naoki Tomono,
Jumpei Uchida,
Yuichiro Miyaoka,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs.
ASP-DAC 2006: 594-599 |
2005 |
8 | EE | Naoki Tomono,
Shunitsu Kohara,
Jumpei Uchida,
Yuichiro Miyaoka,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A processor core synthesis system in IP-based SoC design.
ASP-DAC 2005: 286-291 |
7 | EE | Nozomu Togawa,
Hideki Kawazu,
Jumpei Uchida,
Yuichiro Miyaoka,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations.
ISCAS (4) 2005: 3499-3502 |
6 | EE | Hideki Kawazu,
Jumpei Uchida,
Yuichiro Miyaoka,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis.
IEICE Transactions 88-A(4): 876-884 (2005) |
5 | EE | Nozomu Togawa,
Koichi Tachikake,
Yuichiro Miyaoka,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition.
IEICE Transactions 88-D(7): 1340-1349 (2005) |
2004 |
4 | EE | Yuichiro Miyaoka,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A cosynthesis algorithm for application specific processors with heterogeneous datapaths.
ASP-DAC 2004: 250-255 |
3 | EE | Nozomu Togawa,
Koichi Tachikake,
Yuichiro Miyaoka,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Instruction set and functional unit synthesis for SIMD processor cores.
ASP-DAC 2004: 743-750 |
2002 |
2 | EE | Yuichiro Miyaoka,
Jinku Choi,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.
APCCAS (1) 2002: 171-176 |
2001 |
1 | EE | Yuichiro Miyaoka,
Yoshiharu Kataoka,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Area/delay estimation for digital signal processor cores.
ASP-DAC 2001: 156-161 |