| 2008 |
|---|
| 149 | EE | Chih-Chi Cheng,
Chia-Hua Lin,
Chung-Te Li,
Samuel C. Chang,
Liang-Gee Chen:
iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor.
DAC 2008: 90-95 |
| 148 | EE | Ching-Yen Chien,
Sheng-Chieh Huang,
Shih-Hsiang Lin,
Yu-Chieh Huang,
Yi-Cheng Chen,
Lei-Chun Chou,
Tzu-Der Chuang,
Yu-Wei Chang,
Chia-Ho Pan,
Liang-Gee Chen:
A 100 MHz 1920×1080 HD-Photo 20 frames/sec JPEG XR encoder design.
ICIP 2008: 1384-1387 |
| 147 | EE | Yu-Lin Chang,
Yi-Min Tsai,
Liang-Gee Chen:
A real-time augmented view synthesis system for transparent car pillars.
ICIP 2008: 1972-1975 |
| 146 | EE | Pei-Kuei Tsung,
Chun-Yi Lin,
Wei-Yin Chen,
Li-Fu Ding,
Liang-Gee Chen:
Multiview video hybrid coding system with texture-depth synthesis.
ICME 2008: 1581-1584 |
| 145 | EE | Chia-Ho Pan,
Sheng-Chieh Huang,
I-Hsien Lee,
Chung-Jr Lian,
Liang-Gee Chen:
Scalable video adaptation optimization using soft decision scheme.
ICME 2008: 469-472 |
| 144 | EE | Wei-Yin Chen,
Li-Fu Ding,
Pei-Kuei Tsung,
Liang-Gee Chen:
Architecture design of high performance embedded compression for high definition video coding.
ICME 2008: 825-828 |
| 143 | EE | Yi-Hau Chen,
Tzu-Der Chuang,
Yu-Han Chen,
Chen-Han Tsai,
Liang-Gee Chen:
Frame-parallel design strategy for high definition B-frame H.264/AVC encoder.
ISCAS 2008: 29-32 |
| 142 | EE | You-Ming Tsao,
Ka-Hang Lok,
Yu-Cheng Lin,
Chih-Hao Sun,
Shao-Yi Chien,
Liang-Gee Chen:
A cost effective reconfigurable memory for multimedia multithreading streaming architecture.
ISCAS 2008: 3406-3409 |
| 141 | EE | Jing-Ying Chang,
Tzu-Heng Wang,
Shao-Yi Chien,
Liang-Gee Chen:
Spatial-temporal consistent labeling for multi-camera multi-object surveillance systems.
ISCAS 2008: 3530-3533 |
| 140 | EE | Chen Han Chung,
Yu-Chieh Kao,
Liang-Gee Chen,
Fu-Shan Jaw:
Intelligent Content-Aware Model-Free Low Power Evoked Neural Signal Compression.
PCM 2008: 898-901 |
| 139 | EE | Yi-Hau Chen,
Chih-Chi Cheng,
Tzu-Der Chuang,
Ching-Yeh Chen,
Shao-Yi Chien,
Liang-Gee Chen:
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine.
IEEE Trans. Circuits Syst. Video Techn. 18(1): 98-109 (2008) |
| 138 | EE | Yu-Han Chen,
Tung-Chien Chen,
Chuan-Yung Tsai,
Sung-Fang Tsai,
Liang-Gee Chen:
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder.
Signal Processing Systems 50(1): 1-17 (2008) |
| 137 | EE | Yi-Hau Chen,
Shao-Yi Chien,
Ching-Yeh Chen,
Yu-Wen Huang,
Liang-Gee Chen:
Analysis and Hardware Architecture Design of Global Motion Estimation.
Signal Processing Systems 53(3): 285-300 (2008) |
| 136 | EE | Yi-Hau Chen,
Tung-Chien Chen,
Shao-Yi Chien,
Yu-Wen Huang,
Liang-Gee Chen:
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC.
Signal Processing Systems 53(3): 335-347 (2008) |
| 2007 |
|---|
| 135 | EE | Yu-Lin Chang,
Chih-Ying Fang,
Li-Fu Ding,
Shao-Yi Chien,
Liang-Gee Chen:
Depth Map Generation for 2D-to-3D Conversion by Short-Term Motion Assisted Color Segmentation.
ICME 2007: 1958-1961 |
| 134 | EE | Shao-Yi Chien,
Chi-Sheng Shih,
Mong-Kai Ku,
Chia-Lin Yang,
Yao-Wen Chang,
Tei-Wei Kuo,
Liang-Gee Chen:
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.
ICME 2007: 9 |
| 133 | EE | Pei-Kuei Tsung,
Li-Fu Ding,
Wei-Yin Chen,
Shao-Yi Chien,
Tung-Chien Chen,
Liang-Gee Chen:
System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint.
ISCAS 2007: 1001-1004 |
| 132 | EE | Tung-Chien Chen,
Chuan-Yung Tsai,
Yu-Wen Huang,
Liang-Gee Chen:
Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC.
IEEE Trans. Circuits Syst. Video Techn. 17(2): 242-247 (2007) |
| 131 | EE | T.-C. Chen,
Y.-H. Chen,
S.-F. Tsai,
Shao-Yi Chien,
Liang-Gee Chen:
Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC.
IEEE Trans. Circuits Syst. Video Techn. 17(5): 568-577 (2007) |
| 130 | EE | Chih-Chi Cheng,
Chao-Tsung Huang,
Ching-Yeh Chen,
Chung-Jr Lian,
Liang-Gee Chen:
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. Video Techn. 17(7): 814-822 (2007) |
| 129 | EE | Yu-Wei Chang,
Hung-Chi Fang,
Chun-Chia Chen,
Chung-Jr Lian,
Liang-Gee Chen:
Word-Level Parallel Architecture of JPEG 2000 Embedded Block Coding Decoder.
IEEE Transactions on Multimedia 9(6): 1103-1112 (2007) |
| 2006 |
|---|
| 128 | EE | Tung-Chien Chen,
Chung-Jr Lian,
Liang-Gee Chen:
Hardware architecture design of an H.264/AVC video codec.
ASP-DAC 2006: 750-757 |
| 127 | EE | Liang-Gee Chen:
Dances with multimedia: embedded video codec design.
CASES 2006: 1 |
| 126 | EE | Chuan-Yung Tsai,
Tung-Chien Chen,
Liang-Gee Chen:
Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder.
ICME 2006: 1941-1944 |
| 125 | EE | Wan-Yu Chen,
Yu-Lin Chang,
Hsu-Kuang Chiu,
Shao-Yi Chien,
Liang-Gee Chen:
Real-Time Depth Image based Rendering Hardware Accelerator for Advanced Three Dimensional Television System.
ICME 2006: 2069-2072 |
| 124 | EE | Jing-Ying Chang,
Chao-Chung Cheng,
Shao-Yi Chien,
Liang-Gee Chen:
Relative Depth Layer Extraction for Monoscopic Video by Use of Multidimensional Filter.
ICME 2006: 221-224 |
| 123 | EE | Yu-Han Chen,
Tung-Chien Chen,
Liang-Gee Chen:
Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application.
ICME 2006: 281-284 |
| 122 | EE | Yi-Hau Chen,
Ching-Yeh Chen,
Chih-Chi Cheng,
Liang-Gee Chen:
Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME.
ICME 2006: 365-368 |
| 121 | EE | You-Ming Tsao,
Chi-Ling Wu,
Shao-Yi Chien,
Liang-Gee Chen:
Adaptive tile depth filter for the depth buffer bandwidth minimization in the low power graphics systems.
ISCAS 2006 |
| 120 | EE | Chi-Sun Tang,
Chen-Han Tsai,
Shao-Yi Chien,
Liang-Gee Chen:
Algorithm and hardware architecture design for weighted prediction in H.264/MPEG-4 AVC.
ISCAS 2006 |
| 119 | EE | Chih-Chi Cheng,
Ching-Yeh Chen,
Yi-Hau Chen,
Liang-Gee Chen:
Analysis and VLSI architecture of update step in motion-compensated temporal filtering.
ISCAS 2006 |
| 118 | EE | Chun-Chia Chen,
Yu-Wei Chang,
Hung-Chi Fang,
Liang-Gee Chen:
Analysis of scalable architecture for the embedded block coding in JPEG 2000.
ISCAS 2006 |
| 117 | EE | Yu-Jen Chen,
Chen-Han Tsai,
Liang-Gee Chen:
Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC.
ISCAS 2006 |
| 116 | EE | Ching-Yeh Chen,
Yi-Hau Chen,
Chih-Chi Cheng,
Liang-Gee Chen:
Frame-level data reuse for motion-compensated temporal filtering.
ISCAS 2006 |
| 115 | EE | Tung-Chien Chen,
Yu-Han Chen,
Chuan-Yung Tsai,
Liang-Gee Chen:
Low power and power aware fractional motion estimation of H.264/AVC for mobile applications.
ISCAS 2006 |
| 114 | EE | Li-Fu Ding,
Shao-Yi Chien,
Liang-Gee Chen:
Joint Prediction Algorithm and Architecture for Stereo Video Hybrid Coding Systems.
IEEE Trans. Circuits Syst. Video Techn. 16(11): 1324-1337 (2006) |
| 113 | EE | Yu-Wen Huang,
Bing-Yu Hsieh,
Shao-Yi Chien,
Shyh-Yih Ma,
Liang-Gee Chen:
Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC.
IEEE Trans. Circuits Syst. Video Techn. 16(4): 507-522 (2006) |
| 112 | EE | Ching-Yeh Chen,
Chao-Tsung Huang,
Yi-Hau Chen,
Liang-Gee Chen:
Level C+ data reuse scheme for motion estimation with corresponding coding orders.
IEEE Trans. Circuits Syst. Video Techn. 16(4): 553-558 (2006) |
| 111 | EE | Tung-Chien Chen,
Shao-Yi Chien,
Yu-Wen Huang,
Chen-Han Tsai,
Ching-Yeh Chen,
To-Wei Chen,
Liang-Gee Chen:
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder.
IEEE Trans. Circuits Syst. Video Techn. 16(6): 673-688 (2006) |
| 110 | EE | Yung-Chi Chang,
Wei-Min Chao,
Chih-Wei Hsu,
Liang-Gee Chen:
Platform-Based MPEG-4 SOC Design for Video Communications.
VLSI Signal Processing 42(1): 7-19 (2006) |
| 109 | EE | Shao-Yi Chien,
Bing-Yu Hsieh,
Yu-Wen Huang,
Shyh-Yih Ma,
Liang-Gee Chen:
Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems.
VLSI Signal Processing 42(3): 241-255 (2006) |
| 108 | EE | Yu-Wen Huang,
Ching-Yeh Chen,
Chen-Han Tsai,
Chun-Fu Shen,
Liang-Gee Chen:
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results.
VLSI Signal Processing 42(3): 297-320 (2006) |
| 107 | EE | Yung-Chi Chang,
Chih-Wei Hsu,
Wei-Min Chao,
Liang-Gee Chen:
Interactive Content-aware Video Streaming System with Fine Granularity Scalability.
VLSI Signal Processing 44(1-2): 117-134 (2006) |
| 2005 |
|---|
| 106 | EE | Chung-Jr Lian,
Yu-Wen Huang,
Hung-Chi Fang,
Yung-Chi Chang,
Liang-Gee Chen:
PEG, MPEG-4, and H.264 Codec IP Development.
DATE 2005: 1118-1119 |
| 105 | EE | Ching-Yeh Chen,
Chao-Tsung Huang,
Yi-Hua Chen,
Chung-Jr Lian,
Liang-Gee Chen:
System analysis of VLSI architecture for motion-compensated temporal filtering.
ICIP (3) 2005: 992-995 |
| 104 | EE | Chia-Ping Lin,
Po-Chih Tseng,
Liang-Gee Chen:
Nearly Lossless Content-Dependent Low-Power DCT Design for Mobile Video Applications.
ICME 2005: 1238-1241 |
| 103 | EE | Wan-Yu Chen,
Yu-Lin Chang,
Shyh-Feng Lin,
Li-Fu Ding,
Liang-Gee Chen:
Efficient Depth Image Based Rendering with Edge Dependent Depth Filter and Interpolation.
ICME 2005: 1314-1317 |
| 102 | EE | Tung-Chien Chen,
Yu-Wen Huang,
Chuan-Yung Tsai,
Chao-Tsung Huang,
Liang-Gee Chen:
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC.
ISCAS (2) 2005: 1790-1793 |
| 101 | EE | To-Wei Chen,
Yu-Wen Huang,
Tung-Chien Chen,
Yu-Han Chen,
Chuan-Yung Tsai,
Liang-Gee Chen:
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos.
ISCAS (3) 2005: 2931-2934 |
| 100 | EE | Shih-Way Huang,
Liang-Gee Chen,
Tsung-Han Tsai:
Memory and computationally efficient psychoacoustic model for MPEG AAC on 16-bit fixed-point processors.
ISCAS (4) 2005: 3155-3158 |
| 99 | EE | Yi-Hau Chen,
Ching-Yeh Chen,
Liang-Gee Chen:
Architecture of global motion compensation for MPEG-4 advanced simple profile.
ISCAS (5) 2005: 1798-1801 |
| 98 | EE | Chih-Chi Cheng,
Chao-Tsung Huang,
Po-Chih Tseng,
Chia-Ho Pan,
Liang-Gee Chen:
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.
ISCAS (5) 2005: 5190-5193 |
| 97 | EE | Yu-Wen Huang,
Chia-Lin Lee,
Ching-Yeh Chen,
Liang-Gee Chen:
One-pass computation-aware motion estimation with adaptive search strategy.
ISCAS (6) 2005: 5469-5472 |
| 96 | EE | Li-Fu Ding,
Shao-Yi Chien,
Yu-Wen Huang,
Yu-Lin Chang,
Liang-Gee Chen:
Stereo video coding system with hybrid coding based on joint prediction scheme.
ISCAS (6) 2005: 6082-6085 |
| 95 | EE | Chia-Ho Pan,
I-Hsien Lee,
Sheng-Chieh Huang,
Chih-Chi Cheng,
Chung-Jr Lian,
Liang-Gee Chen:
Application Layer Error Correction Scheme for Video Header Protection on Wireless Network.
ISM 2005: 499-505 |
| 94 | EE | Chi-Sheng Shih,
Chia-Lin Yang,
Mong-Kai Ku,
Tei-Wei Kuo,
Shao-Yi Chien,
Yao-Wen Chang,
Liang-Gee Chen:
Reconfigurable Platform for Content Science Research.
RTCSA 2005: 481-486 |
| 93 | EE | Yu-Lin Chang,
Shyh-Feng Lin,
Ching-Yeh Chen,
Liang-Gee Chen:
Video de-interlacing by adaptive 4-field global/local motion compensated approach.
IEEE Trans. Circuits Syst. Video Techn. 15(12): 1569-1582 (2005) |
| 92 | EE | Yu-Wen Huang,
Bing-Yu Hsieh,
Tung-Chien Chen,
Liang-Gee Chen:
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder.
IEEE Trans. Circuits Syst. Video Techn. 15(3): 378-401 (2005) |
| 91 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method.
IEEE Trans. Circuits Syst. Video Techn. 15(7): 910-920 (2005) |
| 90 | EE | Hung-Chi Fang,
Yu-Wei Chang,
Tu-Chih Wang,
Chung-Jr Lian,
Liang-Gee Chen:
Parallel embedded block coding architecture for JPEG 2000.
IEEE Trans. Circuits Syst. Video Techn. 15(9): 1086-1097 (2005) |
| 89 | EE | Shao-Yi Chien,
Shyh-Yih Ma,
Liang-Gee Chen:
Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements.
IEEE Trans. Circuits Syst. Video Techn. 15(9): 1156-1169 (2005) |
| 88 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform.
IEEE Transactions on Signal Processing 53(4): 1575-1586 (2005) |
| 87 | EE | Pei-Jun Lee,
Homer H. Chen,
Wen-June Wang,
Liang-Gee Chen:
Feature-Based Error Concealment for Object-Based Video.
IEICE Transactions 88-B(6): 2616-2626 (2005) |
| 86 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters.
VLSI Signal Processing 40(2): 175-188 (2005) |
| 85 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization.
VLSI Signal Processing 40(3): 343-353 (2005) |
| 84 | EE | Po-Chih Tseng,
Chao-Tsung Huang,
Liang-Gee Chen:
Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems.
VLSI Signal Processing 41(1): 35-47 (2005) |
| 83 | EE | Yung-Chi Chang,
Chao-Chih Huang,
Wei-Min Chao,
Liang-Gee Chen:
An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System.
VLSI Signal Processing 41(2): 183-191 (2005) |
| 2004 |
|---|
| 82 | | Jing-Kng Chang,
Hung-Chi Fang,
Yen-Wei Huang,
Liang-Gee Chen:
Architecture of MPEG-7 color structure description generator for realtime video applications.
ICIP 2004: 2813-2816 |
| 81 | | Yu-Wen Huang,
Bing-Yu Hsieh,
Tung-Chien Chen,
Liang-Gee Chen:
Hardware architecture design for H.264/AVC intra frame coder.
ISCAS (2) 2004: 269-272 |
| 80 | | Tung-Chien Chen,
Yu-Wen Huang,
Liang-Gee Chen:
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture.
ISCAS (2) 2004: 273-276 |
| 79 | | Ching-Yeh Chen,
Shao-Yi Chien,
Wei-Min Chao,
Yu-Wen Huang,
Liang-Gee Chen:
Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile.
ISCAS (2) 2004: 301-304 |
| 78 | | Siou-Shen Lin,
Po-Chih Tseng,
Liang-Gee Chen:
Low-power parallel tree architecture for full search block-matching motion estimation.
ISCAS (2) 2004: 313-316 |
| 77 | | Yu-Lin Chang,
Shyh-Feng Lin,
Liang-Gee Chen:
Extended intelligent edge-based line average with its implementation and test method.
ISCAS (2) 2004: 341-344 |
| 76 | | Po-Chih Tseng,
Chao-Tsung Huang,
Liang-Gee Chen:
Reconfigurable discrete cosine transform processor for object-based video signal processing.
ISCAS (2) 2004: 353-356 |
| 75 | | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
B-spline factorization-based architecture for inverse discrete wavelet transform.
ISCAS (2) 2004: 829-832 |
| 74 | EE | Yung-Chi Chang,
Chih-Wei Hsu,
Liang-Gee Chen:
MPEG-4 FGS Encoder Design for an Interactive Content-aware MPEG-4 Video Streaming SOC.
IWSOC 2004: 172-175 |
| 73 | EE | Jing-Ying Chang,
Chung-Jr Lian,
Hung-Chi Fang,
Liang-Gee Chen:
Architecture and Analysis of Color Structure Descriptor for Real-Time Video Indexing and Retrieval.
PCM (2) 2004: 130-137 |
| 72 | EE | Yu-Wen Huang,
Shao-Yi Chien,
Bing-Yu Hsieh,
Liang-Gee Chen:
Global elimination algorithm and architecture design for fast block matching motion estimation.
IEEE Trans. Circuits Syst. Video Techn. 14(6): 898-907 (2004) |
| 71 | EE | Shao-Yi Chien,
Yu-Wen Huang,
Bing-Yu Hsieh,
Shyh-Yih Ma,
Liang-Gee Chen:
Fast video segmentation algorithm with shadow cancellation, global motion compensation, and adaptive threshold techniques.
IEEE Transactions on Multimedia 6(5): 732-748 (2004) |
| 2003 |
|---|
| 70 | | Shao-Yi Chien,
Shu-Han Yu,
Li-Fu Ding,
Yun-Nien Huang,
Liang-Gee Chen:
Efficient stereo video coding system for immersive teleconference with two-stage hybrid disparity estimation algorithm.
ICIP (1) 2003: 749-752 |
| 69 | | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank.
ICIP (2) 2003: 571-574 |
| 68 | | Yu-Lin Chang,
Ching-Yeh Chen,
Shyh-Feng Lin,
Liang-Gee Chen:
Motion compensated de-interlacing with adaptive global motion estimation and compensation.
ICIP (3) 2003: 693-696 |
| 67 | | Wei-Min Chao,
Yung-Chi Chang,
Chih-Wei Hsu,
Liang-Gee Chen:
Platform architecture design for MEG-4 video coding.
ICIP (3) 2003: 93-96 |
| 66 | EE | Tsung-Han Tsai,
Shih-Way Huang,
Liang-Gee Chen:
Design of a low power psycho-acoustic model co-processor for MPEG-2/4 AAC LC stereo encoder.
ISCAS (2) 2003: 552-555 |
| 65 | EE | Te-Hao Chang,
Chung-Jr Lian,
Hong-Hui Chen,
Jing-Ying Chang,
Liang-Gee Chen:
Effective hardware-oriented technique for the rate control of JPEG2000 encoding.
ISCAS (2) 2003: 684-687 |
| 64 | EE | Shyh-Feng Lin,
Yu-Lin Chang,
Liang-Gee Chen:
Motion adaptive de-interlacing by horizontal motion detection and enhanced ELA processing.
ISCAS (2) 2003: 696-699 |
| 63 | EE | Shao-Yi Chien,
Ching-Yeh Chen,
Wei-Min Chao,
Yu-Wen Huang,
Liang-Gee Chen:
Analysis and hardware architecture for global motion estimation in MPEG-4 Advanced Simple Profile.
ISCAS (2) 2003: 720-723 |
| 62 | EE | Hung-Chi Fang,
Tu-Chih Wang,
Chung-Jr Lian,
Te-Hao Chang,
Liang-Gee Chen:
High speed memory efficient EBCOT architecture for JPEG2000.
ISCAS (2) 2003: 736-739 |
| 61 | EE | Chih-Wei Hsu,
Yung-Chi Chang,
Wei-Min Chao,
Liang-Gee Chen:
Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder.
ISCAS (2) 2003: 784-787 |
| 60 | EE | Wei-Min Chao,
Tung-Chien Chen,
Yung-Chi Chang,
Chih-Wei Hsu,
Liang-Gee Chen:
Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 Advanced Simple Profile.
ISCAS (2) 2003: 788-791 |
| 59 | EE | Yu-Wen Huang,
Tu-Chih Wang,
Bing-Yu Hsieh,
Liang-Gee Chen:
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264.
ISCAS (2) 2003: 796-799 |
| 58 | EE | Tu-Chih Wang,
Yu-Wen Huang,
Hung-Chi Fang,
Liang-Gee Chen:
Parallel 4/spl times/4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264.
ISCAS (2) 2003: 800-803 |
| 57 | | Shao-Yi Chien,
Shu-Han Yu,
Li-Fu Ding,
Yun-Nien Huang,
Liang-Gee Chen:
Fast disparity estimation algorithm for mesh-based stereo image/video compression with two-stage hybrid approach.
VCIP 2003: 1521-1530 |
| 56 | | Bing-Yu Hsieh,
Yu-Wen Huang,
Tu-Chih Wang,
Shao-Yi Chien,
Liang-Gee Chen:
Fast motion estimation algorithm for H.264/MPEG-4 AVC by using multiple reference frame skipping criteria.
VCIP 2003: 1551-1560 |
| 55 | | Yu-Wen Huang,
Shyh-Yih Ma,
Chun-Fu Shen,
Liang-Gee Chen:
Predictive line search: an efficient motion estimation algorithm for MPEG-4 encoding systems on multimedia processors.
IEEE Trans. Circuits Syst. Video Techn. 13(1): 111-117 (2003) |
| 54 | | Chung-Jr Lian,
Kuan-Fu Chen,
Hong-Hui Chen,
Liang-Gee Chen:
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000.
IEEE Trans. Circuits Syst. Video Techn. 13(3): 219-230 (2003) |
| 53 | | Shao-Yi Chien,
Yu-Wen Huang,
Liang-Gee Chen:
Predictive watershed: a fast watershed algorithm for video segmentation.
IEEE Trans. Circuits Syst. Video Techn. 13(5): 453-461 (2003) |
| 2002 |
|---|
| 52 | EE | Po-Chih Tseng,
Chao-Tsung Huang,
Liang-Gee Chen:
Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method.
APCCAS (1) 2002: 363-366 |
| 51 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform.
APCCAS (1) 2002: 383-388 |
| 50 | EE | Pei-Jun Lee,
Liang-Gee Chen:
Error recovery for MPEG-4 shape and texture information.
APCCAS (1) 2002: 525-528 |
| 49 | EE | Hung-Chi Fang,
Tu-Chih Wang,
Liang-Gee Chen:
Real-time deblocking filter for MPEG-4 systems.
APCCAS (1) 2002: 541-544 |
| 48 | | Shao-Yi Chien,
Ching-Yeh Chen,
Wei-Min Chao,
Chih-Wei Hsu,
Yu-Wen Huang,
Liang-Gee Chen:
A fast and high subjective quality sprite generation algorithm with frame skipping and multiple sprites techniques.
ICIP (1) 2002: 193-196 |
| 47 | | Te-Hao Chang,
Li-Lin Chen,
Chung-Jr Lian,
Hong-Hui Chen,
Liang-Gee Chen:
Computation reduction technique for lossy JPEG2000 encoding through EBCOT Tier-2 feedback processing.
ICIP (3) 2002: 85-88 |
| 46 | EE | Hong-Hui Chen,
Chung-Jr Lian,
Te-Hao Chang,
Liang-Gee Chen:
Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000.
ISCAS (4) 2002: 329-332 |
| 45 | EE | Shao-Yi Chien,
Yu-Wen Huang,
Liang-Gee Chen:
A hardware accelerator for video segmentation using programmable morphology PE array.
ISCAS (4) 2002: 341-344 |
| 44 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method.
ISCAS (5) 2002: 565-568 |
| 43 | | Yu-Wen Huang,
Shao-Yi Chien,
Bing-Yu Hsieh,
Liang-Gee Chen:
Automatic threshold decision of background registration technique for video segmentation.
VCIP 2002: 552-563 |
| 42 | | Po-Chih Tseng,
Chao-Tsung Huang,
Liang-Gee Chen:
VLSI implementation of shape-adaptive discrete wavelet transform.
VCIP 2002: 655-666 |
| 41 | | Tu-Chih Wang,
Hung-Chi Fang,
Liang-Gee Chen:
Low-delay and error-robust wireless video transmission for video communications.
IEEE Trans. Circuits Syst. Video Techn. 12(12): 1049- (2002) |
| 40 | | Shao-Yi Chien,
Shyh-Yih Ma,
Liang-Gee Chen:
Efficient moving object segmentation algorithm using background registration technique.
IEEE Trans. Circuits Syst. Video Techn. 12(7): 577-586 (2002) |
| 39 | | Hao-Chieh Chang,
Yung-Chi Chang,
Yi-Chu Wang,
Wei-Ming Chao,
Liang-Gee Chen:
VLSI architecture design of MPEG-4 shape coding.
IEEE Trans. Circuits Syst. Video Techn. 12(9): 741- (2002) |
| 2001 |
|---|
| 38 | EE | Chung-Jr Lian,
Liang-Gee Chen,
Hao-Chieh Chang,
Yung-Chi Chang:
Design and implementation of JPEG encoder IP core.
ASP-DAC 2001: 29-30 |
| 37 | EE | Liang-Gee Chen,
Chung-Jr Lian,
Kuan-Fu Chen,
Hong-Hui Chen:
Analysis and Architecture Design of JPEG2000.
ICME 2001 |
| 36 | EE | Shao-Yi Chien,
Yu-Wen Huang,
Shyh-Yih Ma,
Liang-Gee Chen:
Automatic Video Segmentation For MPEG-4 Using Predictivewatershed.
ICME 2001 |
| 35 | EE | Yung-Chi Chang,
Chao-Chih Huang,
Hao-Chieh Chang,
Hung-Chi Fang,
Liang-Gee Chen:
Error-Propagation Analysis and Concealment Strategy for MPEG-4 Video Bitstream with Data Partitioning.
ICME 2001 |
| 34 | EE | Hao-Chieh Chang,
Zhong-Lan Yang,
Chung-Jr Lian,
Liang-Gee Chen:
Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding.
ISCAS (2) 2001: 193-196 |
| 33 | EE | Mei-Yun Hsu,
Hao-Chieh Chang,
Yi-Chu Wang,
Liang-Gee Chen:
Scalable module-based architecture for MPEG-4 BMA motion estimation.
ISCAS (2) 2001: 245-248 |
| 32 | EE | Chung-Jr Lian,
Kuan-Fu Chen,
Hong-Hui Chen,
Liang-Gee Chen:
Lifting based discrete wavelet transform architecture for JPEG2000.
ISCAS (2) 2001: 445-448 |
| 31 | EE | Kuan-Fu Chen,
Chung-Jr Lian,
Hong-Hui Chen,
Liang-Gee Chen:
Analysis and architecture design of EBCOT for JPEG-2000.
ISCAS (2) 2001: 765-768 |
| 30 | EE | Shao-Yi Chien,
Yu-Wen Huang,
Shyh-Yih Ma,
Liang-Gee Chen:
A hybrid morphology processing units architecture for real-time video segmentation systems.
ISCAS (5) 2001: 275-278 |
| 29 | | Yi-Chu Wang,
Hao-Chieh Chang,
Wei-Ming Chao,
Liang-Gee Chen:
Efficient architecture of binary motion estimation for MPEG-4 shape coding.
VCIP 2001: 959-967 |
| 28 | | Po-Cheng Wu,
Liang-Gee Chen:
An efficient architecture for two-dimensional discrete wavelet transform.
IEEE Trans. Circuits Syst. Video Techn. 11(4): 536-545 (2001) |
| 27 | | Jun-Fu Shen,
Tu-Chih Wang,
Liang-Gee Chen:
A novel low-power full-search block-matching motion-estimation design for H.263+.
IEEE Trans. Circuits Syst. Video Techn. 11(7): 890-897 (2001) |
| 26 | EE | Chien-Yu Chen,
Zhong-Lan Yang,
Tu-Chih Wang,
Liang-Gee Chen:
A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform.
VLSI Signal Processing 28(3): 151-163 (2001) |
| 25 | EE | Liang-Gee Chen,
Hsueh-Ming Hang,
Ichiro Kuroda:
Guest Editors' Introduction.
VLSI Signal Processing 29(3): 155-156 (2001) |
| 24 | EE | Tsung-Han Tsai,
Ren-Jr Wu,
Liang-Gee Chen:
A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core.
VLSI Signal Processing 29(3): 255-265 (2001) |
| 2000 |
|---|
| 23 | | Shao-Yi Chien,
Shyh-Yih Ma,
Liang-Gee Chen:
Efficient video segmentation algorithm for real-time MPEG-4 camera system.
VCIP 2000: 1087-1098 |
| 22 | EE | Hao-Chieh Chang,
Jiun-Ying Jiu,
Li-Lin Chen,
Liang-Gee Chen:
A Low Power 8 x 8 Direct 2-D DCT Chip Design.
VLSI Signal Processing 26(3): 319-332 (2000) |
| 1999 |
|---|
| 21 | EE | Tsung-Han Tsai,
Liang-Gee Chen:
A cost effective architecture design of inverse quantization and multichannel processing for MPEG-2 audio decoding.
ISCAS (3) 1999: 548-551 |
| 20 | EE | Sheng-Chieh Huang,
Liang-Gee Chen,
Hao-Chieh Chang:
A novel image compression algorithm by using Log-Exp transform.
ISCAS (4) 1999: 17-20 |
| 19 | EE | Jun-Fu Shen,
Liang-Gee Chen,
Hao-Chieh Chang,
Tu-Chih Wang:
Low power full-search block-matching motion estimation chip for H.263+.
ISCAS (4) 1999: 299-302 |
| 18 | EE | Hao-Chieh Chang,
Liang-Gee Chen,
Yung-Chi Chang,
Sheng-Chieh Huang:
A VLSI architecture design of VLC encoder for high data rate video/image coding.
ISCAS (4) 1999: 398-401 |
| 1998 |
|---|
| 17 | | Liang-Gee Chen,
Juing-Ying Jiu,
Hao-Chieh Chang,
Yung-Pin Lee,
Chung-Wei Ku:
A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm.
ASP-DAC 1998: 145-150 |
| 1997 |
|---|
| 16 | EE | Yeong-Kang Lai,
Liang-Gee Chen,
Yung-Pin Lee:
A flexible data-interlacing architecture for full-search block-matching algorithm.
ASAP 1997: 96- |
| 15 | EE | Mei-Juan Chen,
Liang-Gee Chen,
Ruei-Xi Chen:
Error Resilience for Block Loss with Overlapped Motion Compensation.
ICIP (2) 1997: 105- |
| 14 | EE | Yee-Wen Chen,
Liang-Gee Chen,
Mei-Juan Chen:
Jointly Optimal Region-Classified Adaptive Vector Quantization for Very Low Bit Rate Video Coding.
VLSI Signal Processing 17(2-3): 189-200 (1997) |
| 1996 |
|---|
| 13 | EE | Sheng-Chieh Huang,
Liang-Gee Chen,
Thou-Ho Chen:
A 32-bit logarithmic number system processor.
VLSI Signal Processing 14(3): 311-319 (1996) |
| 1995 |
|---|
| 12 | EE | Chun-Te Chen,
Liang-Gee Chen,
Jue-Hsuan Hsiao:
A hardware-oriented design for weighted median filters.
ASP-DAC 1995 |
| 11 | EE | Liang-Gee Chen,
Yeu-Shen Jehng,
Tzi-Dar Chiueh:
Pipeline interleaving design for FIR, IIR, and FFT array processors.
VLSI Signal Processing 10(3): 275-293 (1995) |
| 1994 |
|---|
| 10 | | Chung-Wei Ku,
Liang-Gee Chen,
Tzi-Dar Chiueh,
Her-Ming Jong:
Tree-Structure Architecture and VLSI Implementation for Vector Quantization Algorithms.
ISCAS 1994: 139-142 |
| 9 | | Sheng-Chieh Huang,
Liang-Gee Chen,
Thou-Ho Chen:
The Chip Design of A 32-b Logarithmic Number System.
ISCAS 1994: 167-170 |
| 8 | | Her-Ming Jong,
Liang-Gee Chen,
Tzi-Dar Chiueh:
Parallel Architectures of 3-Step Search Block-Matching Algorithm for Video Coding.
ISCAS 1994: 209-212 |
| 7 | | Jue-Hsuan Hsiao,
Liang-Gee Chen,
Tzi-Dar Chiueh,
Chun-Te Chen:
High Throughput CORDIC-Based Systolic Array Design for the Discrete Cosine Transform.
ISCAS 1994: 85-88 |
| 6 | EE | Lih-Gwo Jeng,
Liang-Gee Chen:
Rate-optimal DSP synthesis by pipeline and minimum unfolding.
IEEE Trans. VLSI Syst. 2(1): 81-88 (1994) |
| 1993 |
|---|
| 5 | | Pinhong Chen,
Jyuo-Min Shyu,
Liang-Gee Chen:
Hardware Verification Using Symbolic State Transition Graphs.
ICCD 1993: 54-57 |
| 4 | | Jue-Hsuan Hsiao,
Liang-Gee Chen,
Tzi-Dar Chiueh,
Chun-Te Chen:
Novel Systolic Array Design for the Discrete Hartley Transform with High Throughput Rate.
ISCAS 1993: 1567-1570 |
| 3 | | Lih-Gwo Jeng,
Liang-Gee Chen:
Rate-Optimal DSP Synthesis by Pipeline and Minimum Undolding.
VLSI Design 1993: 148-153 |
| 1992 |
|---|
| 2 | | Thou-Ho Chen,
Liang-Gee Chen,
Yi-Shing Chang:
Design of Concurrent Error-Detectable VLSI-Based Array Dividers.
ICCD 1992: 72-75 |
| 1991 |
|---|
| 1 | | Liang-Gee Chen,
Wai-Ting Chen,
Yeu-Shen Jehng,
Tzi-Dar Chiueh:
A Predictive Parallel Motion Estimation Algorithm for Digital Image Processing.
ICCD 1991: 617-620 |
